Curved Through-Via Sidewalls for Reliable IC Package Interfaces
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing stress concentrations at the interfaces between through vias and encapsulants, leading to delamination and cracking issues in integrated circuit packages, which affect the reliability of the packages.
Innovation Solution
Forming through vias with curved sidewalls, such as hourglass or bulged rectangle shapes, to distribute stress more evenly and reduce the risk of delamination and cracking at the via-encapsulant interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are formed with straight sidewalls, then the manufacturing process is simple, but stress concentrations occur at the via-encapsulant interfaces leading to delamination and cracking
Solution Approach 1:
The patent applies curvature to the sidewalls of through vias, transitioning from straight sidewalls to curved sidewalls with specific radii. This curvature distributes stress more evenly at the via-encapsulant interfaces, preventing stress concentration that leads to delamination and cracking. The curved geometry is achieved through controlled etching processes with specific aspect ratios and radii of curvature.
Solution Approach 2:
The patent changes geometric parameters of the through vias, specifically the sidewall curvature radius and aspect ratio. By optimizing these parameters, the stress distribution at the interfaces is improved while maintaining manufacturability. The specific parameter ranges are defined to balance reliability improvement with manufacturing complexity.
2Strength
If through vias are formed with curved sidewalls, then stress concentrations are reduced and delamination risk decreases, but the manufacturing process becomes more complex
Solution Approach 1:
The curved sidewalls are formed using controlled etching processes that create specific radius of curvature profiles. This curvature strengthens the via-encapsulant interfaces by distributing mechanical stress, while the etching process parameters are optimized to achieve the desired curvature without excessive process complexity.
Solution Approach 2:
Specific geometric parameters such as sidewall curvature radius and etch aspect ratio are optimized to achieve the desired stress distribution. These parameter changes are implemented within standard manufacturing capabilities, balancing interface strength improvement with manufacturing feasibility.
3Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but packaging challenges increase and reliability decreases
Solution Approach 1:
As integration density increases and feature sizes decrease, the curved sidewall design becomes increasingly important for maintaining reliability. The curvature provides stress distribution benefits that are critical when via dimensions are reduced, preventing the miniaturization process from compromising package integrity.
Solution Approach 2:
The via geometry parameters are scaled and optimized for smaller feature sizes. As minimum feature size is reduced to increase integration density, the sidewall curvature radius and other geometric parameters are adjusted proportionally to maintain adequate stress distribution and prevent delamination in miniaturized packages.
Data Source
AI summary
In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.