Curved Via Capping for Low-Resistance Backend Interconnects
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Solution Overview
Problem
As semiconductor components shrink in size, the challenge of reducing contact resistance in vias within backend interconnect structures becomes significant, impacting the performance and integration density of electronic devices.
Innovation Solution
A capping layer with a curved upper surface is selectively formed on vias to increase the contact area, accompanied by an inhibitor layer that impedes the uniform deposition of barrier and liner layers, resulting in non-uniform thicknesses that reduce contact resistance while maintaining protection against material diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If component size is reduced to increase integration density, then more components can be integrated into a given area, but contact resistance in vias increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform barrier layer thickness through selective inhibition. The inhibitor layer is deposited only on specific surfaces (horizontal surfaces like interlayer dielectric tops), while vertical via surfaces remain uninhibited. This results in the barrier layer being thinner on via surfaces and thicker on horizontal surfaces, locally optimizing electrical contact properties where needed while maintaining protection elsewhere.
Solution Approach 2:
The inhibitor layer is deposited in advance before the barrier layer formation. This preliminary action prepares the surface by selectively blocking deposition sites, ensuring that when the barrier layer is subsequently deposited, it automatically forms with the desired non-uniform thickness pattern without requiring additional processing steps.
2Reliability
If barrier layer thickness is reduced to decrease contact resistance, then electrical performance improves, but protection against material diffusion decreases
Solution Approach 1:
The barrier layer is engineered with spatially varying thickness: thin on vertical via surfaces to minimize contact resistance, and thick on horizontal surfaces to provide robust diffusion protection. This local differentiation allows simultaneous optimization of electrical performance and chemical protection in different locations.
Solution Approach 2:
The inhibitor layer acts as an intermediary that controls the barrier layer deposition process. By selectively blocking certain surfaces during barrier layer formation, the inhibitor mediates between the conflicting requirements of low contact resistance and high diffusion protection, enabling the barrier layer to self-organize into the optimal non-uniform thickness pattern.
3Object-affected harmful factors
If uniform barrier layer is deposited to maintain consistent protection, then diffusion protection is ensured, but contact resistance increases
Solution Approach 1:
The inhibitor layer is deposited beforehand to pre-mark which surfaces should receive barrier layer protection and which should not. This preliminary surface modification enables the subsequent barrier layer deposition to automatically create the desired non-uniform pattern, resolving the contradiction between uniform protection and low contact resistance.
Solution Approach 2:
The barrier layer transitions from a uniform structure to a locally optimized structure through the inhibitor's selective action. The resulting non-uniform thickness distribution provides thin barriers where low resistance is needed and thick barriers where diffusion protection is critical, achieving local quality optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases contact resistance and enhances the integration density of semiconductor devices by improving electrical performance and reducing material diffusion, while being compatible with existing manufacturing processes.
Implementation Method 1
The capping layer has a curved upper surface to increase the surface area of the interface between the via and a subsequently formed conductive line overlying the via. The increased surface area reduces the contact resistance of the via.
Implementation Method 2
an inhibitor layer is selectively formed on the capping layer. The inhibitor layer impedes the subsequent formation of a barrier layer and a liner layer over the capping layer.
Data Source
AI summary
A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.