Curved Wafer Processing for Enhanced Carrier Mobility
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Solution Overview
Problem
Current semiconductor manufacturing techniques fail to effectively induce optimal stress in channel regions of MOS transistors, limiting carrier mobility and device performance.
Innovation Solution
The method involves curving the processing surface of a substrate during semiconductor fabrication to grow stress-inducing epitaxial layers, such as SiGe for compressive stress in PMOS devices and SiC for tensile stress in NMOS devices, which increases hole and electron mobility by altering the lattice structure and volume of recesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar wafer processing is used, then manufacturing simplicity is maintained, but carrier mobility and device performance are limited due to insufficient stress induction in channel regions
Solution Approach 1:
The patent applies curvature to the wafer surface by mounting it on a curved substrate holder, creating a non-planar processing surface. This curvature enables the formation of recesses with curved bottoms that generate enhanced stress in the channel regions during epitaxial growth, thereby improving carrier mobility and device performance without fundamentally changing the manufacturing process flow
Solution Approach 2:
The patent creates localized stress regions by forming recesses at specific locations on the wafer surface where channel regions will be formed. The curved bottom of these recesses provides localized tensile or compressive stress depending on the curvature direction, enabling targeted stress induction in NMOS or PMOS devices respectively, while leaving other regions of the wafer unaffected
2Reliability
If stress-inducing epitaxial layers are grown to improve carrier mobility, then device performance increases, but the manufacturing process becomes more complex compared to traditional planar methods
Solution Approach 1:
The curved substrate holder creates a non-planar processing surface that naturally forms recesses with curved bottoms during epitaxial growth. This curvature geometry inherently generates stress in the channel regions without requiring additional stress-inducing layers or complex process steps, making the stress induction an integrated part of the standard epitaxial growth process
Solution Approach 2:
The patent changes the geometric parameter of the wafer surface from planar to curved by using a curved substrate holder. This parameter change in surface topology directly influences the stress distribution during epitaxial growth, enabling stress induction through geometric configuration rather than material composition changes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility by creating greater stress in the channel regions than traditional planar wafer processes, improving transistor performance and efficiency.
Implementation Method 1
grow stress-inducing epitaxial layers, such as SiGe for compressive stress in PMOS devices and SiC for tensile stress in NMOS devices, which increases hole and electron mobility by altering the lattice structure and volume of recesses
Data Source
AI summary
An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.