3-D Memory Arrays With Curvilinear Gate Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Vertically oriented memory cell strings in flash memory arrays face challenges in reducing horizontal substrate area while maintaining packing density, as they often increase vertical thickness, leading to horizontal packing density considerations not present in horizontally oriented layouts.
Innovation Solution
A 3-D memory array design featuring elevationally extending strings of memory cells with select devices having nested longitudinally curvilinear gate lines laterally separated by dielectric material, allowing for reduced block height and optimized pitch between gate lines, enabling efficient use of substrate space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cell strings are oriented vertically to reduce horizontal substrate area, then horizontal area is reduced, but vertical thickness increases creating packing density considerations
Solution Approach 1:
The patent transitions from traditional 2D horizontal memory cell arrangement to 3D vertical stacking, extending memory cells in the vertical dimension (z-axis) while maintaining horizontal integration. This dimensional change allows increased storage capacity without proportionally increasing horizontal substrate area, effectively resolving the contradiction between reducing horizontal area and managing vertical thickness through sophisticated 3D spatial organization.
Solution Approach 2:
The patent implements nested structures where select devices, charge storage regions, and memory cells are arranged in concentric or layered configurations. The select device surrounds the charge storage region which in turn surrounds the memory cell string, creating a compact nested architecture that maximizes vertical space utilization while maintaining controlled vertical thickness and improved horizontal packing density.
2Quantity of substance
If vertically extending memory cell strings are implemented, then horizontal packing density improves, but fabrication complexity increases
Solution Approach 1:
The patent divides the memory structure into distinct functional segments: memory cell strings, charge storage regions, select devices, and word line structures. Each segment is fabricated and positioned independently through sequential processing steps, allowing complex 3D vertical structures to be built from simpler modular components, thereby managing fabrication complexity while achieving high horizontal packing density.
Solution Approach 2:
The patent employs preliminary formation of certain structures before others, such as pre-forming the substrate structure and initial layers before adding vertical memory cell strings and select devices. This staged fabrication approach with preliminary actions simplifies the overall manufacturing process by breaking down complex 3D fabrication into manageable sequential steps.
Data Source
AI summary
A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.