Voltage-Aware Delay Margin Tuning for Custom Circuit Timing
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Solution Overview
Problem
Dynamic voltage scaling in integrated circuits can lead to timing issues between signal paths, causing functional failures due to changes in power supply voltage levels, which existing technologies fail to adequately address.
Innovation Solution
The implementation of delay units within circuit paths that monitor and adjust voltage levels, pausing and resuming operations to adjust delay amounts in response to changes in power supply voltage, ensuring adequate timing margins across varying voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage scaling is applied to reduce power consumption, then energy efficiency is improved, but timing integrity between signal paths deteriorates causing functional failures
Solution Approach 1:
The patent implements dynamic delay adjustment mechanisms that automatically adapt to changing voltage conditions. Delay elements are configured to provide variable delay amounts based on detected voltage levels, ensuring timing integrity is maintained across different power supply conditions while allowing dynamic voltage scaling to operate
Solution Approach 2:
The patent employs feedback circuits that monitor voltage levels and use this information to adjust delay amounts in real-time. The feedback mechanism detects voltage changes and dynamically modifies the timing characteristics of signal paths to compensate for voltage-induced timing variations, preventing functional failures
2Reliability
If delay units are added to adjust timing margins, then timing integrity is improved, but device complexity increases
Solution Approach 1:
The patent divides the circuit into multiple segments with independently adjustable delay elements. Each segment can be tuned separately to provide the necessary timing margin, allowing precise control without requiring complex global adjustment mechanisms. This segmentation approach reduces overall complexity by localizing timing adjustments
Solution Approach 2:
The patent utilizes delay elements whose delay characteristics can be dynamically changed based on voltage conditions. By changing the delay parameter rather than adding complex control logic, the system maintains timing integrity with minimal additional circuitry. The delay amount is adjusted as a variable parameter in response to voltage detection
Data Source
AI summary
Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed.