Custom Compute Cores for Parallel Pattern Recognition
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Solution Overview
Problem
Conventional computing systems face inefficiencies in pattern recognition tasks due to the need to search large volumes of data for multiple patterns, leading to processing bottlenecks and resource underutilization, particularly in systems emulating biological brain hierarchies.
Innovation Solution
The implementation of custom compute cores within integrated circuit devices, utilizing finite state machine lattices and programmable logic to perform pre- and post-processing tasks, allowing for efficient data compression, organization, and pattern recognition similar to biological systems, thereby alleviating processor burdens and enhancing processing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional von Neumann based computers are used for pattern recognition, then the system is simple to implement, but the processing efficiency deteriorates due to bottlenecks in searching large volumes of data for multiple patterns
Solution Approach 1:
The system segments pattern recognition into multiple hierarchical levels, with lower layers analyzing raw signals and higher layers analyzing signal outputs from lower levels. This segmentation allows parallel processing of different pattern types simultaneously, improving productivity while distributing complexity across modular layers
Solution Approach 2:
The patent transitions from conventional sequential von Neumann architecture to a hierarchical parallel architecture inspired by biological brains. This dimensional change in system organization enables simultaneous multi-pattern recognition across hierarchical levels, dramatically improving pattern recognition efficiency without simple linear scaling
2Speed
If a large number of circuits operate in parallel to search data streams, then the processing speed improves, but the intermediate results become larger than the original input data, causing memory and bandwidth issues
Solution Approach 1:
The system extracts only the essential pattern match results from parallel circuit operations rather than processing all intermediate outputs. By taking out only the relevant pattern detection outcomes, the system maintains high processing speed while minimizing intermediate data volume that needs to be transmitted and stored
Solution Approach 2:
Lower hierarchical layers perform preliminary pattern analysis on raw signals before passing results to higher layers. This preliminary action filters and pre-processes data in advance, reducing the volume of intermediate results that need to be handled by subsequent processing stages
3Ease of operation
If multiple patterns are searched one at a time in a data stream, then the system uses simple sequential processing, but the delay increases with the number of patterns, slowing down data receipt
Solution Approach 1:
The system merges multiple pattern search operations into a unified hierarchical processing framework where different patterns are searched simultaneously across parallel circuits at various hierarchical levels. This combining of operations eliminates sequential delays while maintaining coordinated processing through the hierarchical structure
Data Source
AI summary
A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.