Custom FSM Engines for Extensible Processor Control
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Solution Overview
Problem
Extensible processors require significant design effort and resources to implement software instruction streams for initiating definable function blocks and external function units, limiting their efficiency and versatility.
Innovation Solution
The implementation of custom instruction control logic engines or finite state machine engines that allow configuration of extensible processors without the need for software instruction streams, enabling automatic generation of control states and data paths to execute instructions directly within the processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software instruction streams are used to initiate definable function blocks and external function units, then the processor can be configured for specific applications, but the design complexity and development time increase significantly
Solution Approach 1:
The patent replaces software-based control streams with a hardware-based finite state machine (FSM) control engine. The FSM is embedded directly in the processor architecture and automatically generates control signals for definable function blocks, eliminating the need for complex software instruction streams and reducing design complexity while maintaining configurability.
Solution Approach 2:
The finite state machine control engine is self-contained and automatically manages the initiation and coordination of definable function blocks and external function units. Once configured, the FSM autonomously generates the necessary control signals without requiring external software intervention, simplifying the overall system design.
2Use of energy by moving object
If ASIPs are designed with specialized instructions for optimized performance, then power consumption is reduced, but the design process becomes time-consuming and costly
Solution Approach 1:
The processor architecture is segmented into standardized functional components including the base ISA execution pipeline, configurable function blocks, and definable function blocks. This modular segmentation allows specialized instructions to be added without redesigning the entire processor, reducing design time while maintaining power efficiency.
Solution Approach 2:
The processor incorporates dynamic configuration capabilities where the finite state machine control engine can adaptively select and execute different instruction sets based on the specific application requirements. This allows the system to optimize power consumption for each application while using a unified, easier-to-design architecture.
3Productivity
If extensible processors are configured with custom instructions for specific applications, then application performance is improved, but the complexity of implementing control logic increases
Solution Approach 1:
The patent replaces complex software-based control logic with a hardware-implemented finite state machine that automatically generates control signals. This substitution reduces the complexity of implementing custom instructions while maintaining or improving application performance through dedicated hardware control.
Solution Approach 2:
The finite state machine control engine serves as a universal control mechanism that can manage various types of function blocks and external units through a standardized interface. This multi-functionality reduces control logic complexity by providing a single, reusable control framework for different application configurations.
Data Source
AI summary
An extensible processor can include an execution pipeline, one or more extensible control engines and architectural visible control states. The extensible processor can be configured to determine a control state of the one or more extensible control engines from the architectural visible control states. The extensible processor can be further configured to initiate execution of a given one of the extensible control engines when a control state in the architectural visible control states corresponding to the given one of the extensible control engines is enabled, wherein the given one of the extensible control engines comprises control input and control outputs based on one or more control transitions of an instruction. The extensible processor can also be further configured to output a result of execution of the given one of the extensible control engines to the architectural visible control states.


