Custom RISC Processor Architecture With Hazard-Aware Pipeline Tuning
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Solution Overview
Problem
Integrated circuits with dedicated microprocessor circuitry often have unused features, and general-purpose programmable processors are inefficient for tasks like digital signal processing, where parallel operations are needed, leading to suboptimal performance.
Innovation Solution
The use of processor generator tools to create a customized RISC processor on a programmable integrated circuit, allowing users to specify parameters like data word size, instruction formats, and pipeline settings, and to analyze and mitigate hazards, resulting in an optimized processor architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dedicated full-featured microprocessor is used on a PLD, then processing speed for certain tasks is improved, but device complexity and resource waste increase
Solution Approach 1:
The patent extracts only the necessary features and functions needed for specific tasks from a full-featured microprocessor, rather than implementing the complete processor. This allows the system to achieve high processing speed for targeted operations while avoiding the complexity and resource waste of unused microprocessor features.
Solution Approach 2:
The patent implements different processing capabilities in different regions of the PLD - dedicated hard-wired logic for speed-critical functions and programmable logic for other tasks. This local differentiation optimizes processing speed where needed while maintaining overall system efficiency and reducing unnecessary complexity.
2Adaptability or versatility
If a general-purpose programmable processor is used, then adaptability is improved, but processing efficiency for parallel operations deteriorates
Solution Approach 1:
The patent merges general-purpose programmable logic with dedicated hard-wired functional units into a hybrid processor architecture. This combination provides the adaptability of programmable processors while incorporating the parallel processing efficiency of dedicated hardware for specific operations like DSP and VLIW processing.
Solution Approach 2:
The patent creates a multi-functional processing system where programmable logic regions can be configured for different tasks while dedicated functional units provide universal parallel processing capabilities for common operations. This universal design maintains adaptability across applications while ensuring efficient parallel processing performance.
3Adaptability or versatility
If unused features of a dedicated microprocessor are included, then future flexibility is improved, but resource waste increases
Solution Approach 1:
The patent segments the processor into modular components - essential functional units implemented in hard logic for immediate performance needs, and programmable logic regions that can be configured for future or varying requirements. This segmentation provides future flexibility only where needed while minimizing resource waste in core processing functions.
4Speed
If more pipeline stages are inserted into soft logic components, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic pipeline configuration where the number of pipeline stages in soft logic components can be adjusted based on performance requirements. This dynamic approach allows optimization of processing speed for critical paths while maintaining simpler configurations for less demanding operations, balancing speed improvements against device complexity.
Data Source
AI summary
A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.