Cut Epitaxial Source Drain Process for Semiconductor Integration
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Solution Overview
Problem
As semiconductor devices scale down, the challenge of preventing epitaxial source/drain (EPI) features from merging becomes more significant, leading to short circuit defects and reduced device integration, as larger EPIs are desired for electrical performance but prone to accidental contact and merging.
Innovation Solution
A cut EPI process is applied to separate merged or closely spaced EPI features, allowing for denser fin placement and larger S/D EPI growth, while maintaining adequate spacing to prevent short circuits, involving anisotropic etching and selective processes to minimize loss of isolation structures and hard masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large epitaxial source/drain features are grown to reduce contact resistance, then electrical performance is improved, but spacing requirements increase causing reduced device integration and potential merging of features
Solution Approach 1:
The patent applies segmentation by dividing the epitaxial growth process into two distinct stages: a first epitaxial growth stage that forms initial source/drain features, and a second epitaxial growth stage that forms additional source/drain features. This segmentation allows each stage to be optimized independently, enabling the formation of large epitaxial features with adequate spacing control to prevent merging while maintaining high device integration density.
2Reliability
If spacing among source/drain features is increased to prevent merging, then short circuit defects are reduced, but device integration density decreases
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before the epitaxial growth process. This mandrel serves as a pre-established template that defines the precise spacing and positioning of source/drain features. By performing this preliminary structuring action, the subsequent epitaxial growth can proceed with controlled spacing that prevents merging while maximizing device integration, as the mandrel already establishes the correct geometric constraints.
3Productivity
If device geometry is scaled down to increase functional density, then production efficiency is improved, but the complexity of preventing EPI merging increases
Solution Approach 1:
The patent applies local quality by implementing different process conditions and parameters for different stages of epitaxial growth. The first epitaxial growth stage uses specific temperature, pressure, and precursor conditions optimized for initial feature formation, while the second stage uses different conditions optimized for additional feature formation. This localized optimization of process quality at different stages allows scaling down to higher functional density while managing processing complexity through stage-specific parameter control rather than uniform complex processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances yield and allows for more densely packed fins, reducing EPI merging defects, improving device reliability and contact formation, and enabling further scaling in semiconductor fabrication.
Implementation Method 1
epitaxially growing two source/drain features in the two source/drain trenches respectively
Implementation Method 2
performing a cut process to the two source/drain features... involving anisotropic etching
Data Source
AI summary
A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.