Cut Metal Gate Air Spacers for Sub-10nm Feature Precision
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in the fabrication process that need to be addressed to maintain efficiency and precision.
Innovation Solution
A method is developed for forming air spacers within a cut metal gate process, involving multiple deposition and etching steps to create precise features on semiconductor fins, using materials like silicon nitride and high-k dielectrics, and employing advanced etching techniques to form gate stacks and spacers, ensuring accurate patterning and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and process control become more difficult to maintain
Solution Approach 1:
The patent segments the gate formation process into multiple discrete steps: forming a mandrel structure, depositing first and second spacers, performing selective etching, and creating air gaps. This segmentation allows each step to be optimized independently for precision while contributing to the overall miniaturization goal, enabling feature sizes below 10nm to be achieved with controlled manufacturing precision
Solution Approach 2:
The patent introduces vertical dimensionality by forming three-dimensional FinFET structures and using vertical spacers extending from the mandrel. This dimensional transition from planar to vertical architecture enables increased integration density while maintaining manufacturable feature dimensions through the exploitation of vertical space rather than further lateral miniaturization
2Manufacturing precision
If advanced etching techniques are used to form precise gate stacks and spacers, then component alignment and patterning precision improve, but device complexity and process steps increase
Solution Approach 1:
The patent performs preliminary actions by pre-forming the mandrel structure and depositing spacers before the actual gate etching process. The first and second spacers are deposited and patterned in advance to define the precise locations where etching will occur, which simplifies the subsequent etching steps and improves alignment precision without requiring complex real-time process control
Solution Approach 2:
The patent uses intermediary materials including the mandrel structure, first spacers, and second spacers as mediators to transfer the pattern from lithography to the final gate structure. These intermediary elements enable precise patterning by serving as temporary masks and alignment references that guide the etching process, reducing the direct complexity of the etching steps themselves
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the precision and integration density of semiconductor devices by allowing for smaller feature sizes and improved component alignment, thereby improving device performance and reliability.
Implementation Method 1
depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate
Implementation Method 2
patterning the various material layers using lithography to form circuit components and elements thereon
Data Source
AI summary
A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.