Cut Metal Gate Refill With Flexible Buffer Layer for FinFET Isolation
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in maintaining the integrity and reproducibility of isolation regions between FinFET transistors, leading to deformation and reduced performance due to stress between dielectric materials and neighboring gates and substrates.
Innovation Solution
The use of a flexible liner material is introduced to reduce stress between dielectric material, neighboring replacement gates, and the underlying substrate, allowing for improved deposition of dielectric material and formation of smaller, more reproducible isolation regions by cutting replacement gates instead of dummy gates, and depositing a stress reduction liner to minimize tapering and stress effects during dielectric fill deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If replacement gates are cut to form isolation regions, then integration density and component miniaturization are improved, but stress between dielectric materials and neighboring gates/substrates causes deformation and reduces reliability
Solution Approach 1:
The isolation region is segmented into multiple functional layers: a rigid dielectric material layer for structural isolation and a flexible liner material layer for stress management. This segmentation allows each layer to perform its specialized function, resolving the contradiction between miniaturization and stress-induced deformation.
Solution Approach 2:
The patent changes the physical parameters of the isolation region by introducing a flexible liner material with specific mechanical properties (flexibility, stress-absorbing characteristics) that differ from the rigid dielectric material. This parameter change enables the isolation region to maintain integrity under stress while supporting continued miniaturization.
2Manufacturing precision
If rigid dielectric material is deposited to fill trenches, then isolation effectiveness is improved, but stress-induced tapering and seam formation occur reducing manufacturing precision
Solution Approach 1:
The flexible liner material acts as an intermediary between the rigid dielectric material and the trench walls. It mediates the stress interactions, allowing the dielectric material to be deposited without causing tapering or seams, thus maintaining both isolation effectiveness and shape uniformity.
Solution Approach 2:
A thin film of flexible liner material is applied to the trench surfaces before filling with rigid dielectric material. This flexible film prevents stress-induced deformation during deposition, eliminating tapering and seam formation while maintaining precise control over the isolation region geometry.
3Area of stationary object
If minimum feature size is reduced to increase integration density, then more components per area are achieved, but stress effects and deformation increase reducing device performance
Solution Approach 1:
The flexible liner material forms a protective thin film around the isolation region, absorbing and distributing mechanical stresses that would otherwise cause deformation. This enables continued reduction of minimum feature size while maintaining device performance by preventing stress-related harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the deposition of dielectric material, reduces deformation, and improves the uniformity and performance of FinFET devices by minimizing stress-induced tapering and seam formation in isolation regions, leading to more reliable and efficient transistor operation.
Implementation Method 1
the first dielectric material reduces stresses exerted between the second dielectric material and the substrate
Implementation Method 2
conformally depositing a first dielectric material on surfaces in the trench
Data Source
AI summary
A method includes etching a gate stack to form a trench extending through the gate stack, the gate stack including a metal gate electrode and a gate dielectric, wherein forming the trench removes a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion; extending the trench through an isolation region under the gate stack and into a semiconductor substrate under the isolation region; conformally depositing a first dielectric material on surfaces in the trench; and depositing a second dielectric material on the first dielectric material to fill the trench, wherein the first dielectric material is a more flexible material than the second dielectric material.