Via-Shaped Cut Gate Structures for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, issues such as parasitic capacitance arise during dielectric refilling after patterning, which is unfavorable for AC applications.
Innovation Solution
The formation of via-shaped cut gate structures using a self-aligned patterning process, involving a protective layer over the ILD layer and recess etching, minimizes parasitic capacitance by forming dielectric structures within gate sidewall spacers without extending into the ILD layer or between neighboring source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric refilling is performed after patterning to maintain structural integrity, then manufacturing reliability is improved, but parasitic capacitance increases which degrades AC performance
Solution Approach 1:
The patent extracts the harmful dielectric material from the region between source/drain regions by forming via openings that remove this material. This eliminates the source of parasitic capacitance while preserving the necessary dielectric structures in other critical areas, thus resolving the contradiction between structural integrity and parasitic capacitance reduction
Solution Approach 2:
The gate structure is segmented into multiple portions with dielectric material selectively removed between source/drain regions. This segmentation allows the dielectric to be present where structural support is needed while being absent where parasitic capacitance would degrade AC performance
2Productivity
If feature sizes are reduced to increase integration density, then productivity is improved, but manufacturing precision requirements increase due to additional process complexities
Solution Approach 1:
The patent performs preliminary patterning actions to define via openings before final gate structure formation. This preliminary action establishes precise alignment references that guide subsequent processing steps, ensuring that even as feature sizes shrink, the required manufacturing precision is maintained through pre-planned, pre-positioned structural elements
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor device with via-shaped cut gate structures. The via shaped cut-gate structures may be formed by a self-aligned patterning process and may minimize parasitic capacitance in the semiconductor device. In some embodiments, a protective layer is deposited over the ILD layer to achieve the self-aligned patterning process. In some embodiments, the protective layer may be formed by recess etching the ILD layer between gate structures and filling the recess with a dielectric layer. In some embodiments, the protective layer may include silicon nitride.