FinFET Contact Patterning With Cut Masks to Limit Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased parasitic capacitance, which can hinder performance in applications like ring oscillators, where reducing this capacitance is crucial for improved performance.
Innovation Solution
The use of a cut mask and a line mask in combination to define regions for contact formation in a dielectric layer, with trim portions that exclude unused areas, thereby avoiding the formation of parasitic capacitance by reducing dummy contacts, is employed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but parasitic capacitance increases which hinders performance
Solution Approach 1:
The patent extracts and removes dummy contacts from the device structure by using trim portions on masks to define precise contact formation regions. This elimination of unnecessary conductive elements directly reduces parasitic capacitance while maintaining the high integration density achieved through small feature sizes.
Solution Approach 2:
The patent applies local quality by creating non-uniform contact distributions through trim portions on masks. Different regions of the device have different contact patterns - active regions have contacts while dummy regions are excluded - thereby locally optimizing electrical characteristics to reduce parasitic capacitance in specific areas without compromising overall integration density.
2Ease of manufacture
If dummy contacts are formed in unused areas, then contact formation process is simplified, but parasitic capacitance increases which reduces performance in applications like ring oscillators
Solution Approach 1:
The patent applies preliminary action by incorporating trim portions on masks before the contact formation process. These trim portions pre-defide which areas should exclude contacts, allowing the contact formation process to proceed uniformly across the wafer while automatically avoiding dummy contact creation in unused regions, thus maintaining manufacturing simplicity without sacrificing device performance.
Solution Approach 2:
The patent uses local quality by creating spatially varying contact patterns through mask trim portions. The trim portions selectively exclude contact formation in dummy regions while allowing contacts in active regions, thereby locally optimizing the device structure to reduce parasitic capacitance without complicating the overall contact formation process.
Data Source
AI summary
An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.