Cut Mask Segmentation for Sub-Lithographic Diffusion Contact Spacing
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Solution Overview
Problem
The semiconductor industry faces limitations in reducing the spacing between semiconductor device features due to the practical performance capabilities of photolithographic tools, leading to spacing violations in design rule checks, which restrict the miniaturization of semiconductor devices and increase manufacturing costs.
Innovation Solution
The approach involves merging separate diffusion contacts into a combined region, forming a cut mask layer, and using an etch process to remove a portion of the combined region, allowing for a narrower gap width than previously achievable, thereby overcoming spacing violations and reducing the area required for semiconductor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the separation width between two diffusion contacts is reduced to achieve smaller transistor size, then the area of the semiconductor device is reduced, but a spacing violation is generated by the design rule check tool
Solution Approach 1:
The patent divides the combined diffusion contact region into multiple segments by introducing a cut mask layer with openings. This segmentation allows the region to be processed in discrete sections, enabling the formation of narrow gaps between contacts that would otherwise violate design rules. The cut mask layer creates distinct zones that can be independently patterned and etched to achieve the desired close spacing.
Solution Approach 2:
The patent introduces an additional dimensional layer by placing a cut mask layer above the combined diffusion contact region. This extra dimension allows for the creation of vertical structures and multi-layer patterning that enables sub-lithographic spacing. The cut mask layer provides a new degree of freedom in the fabrication process to achieve spacings smaller than the photolithographic resolution limit.
2Productivity
If the spacing between conductive traces is reduced to increase device density, then more functionality is achieved on smaller chip area, but photolithographic tools cannot resolve the tight spacing
Solution Approach 1:
The patent segments the patterning process into multiple steps using different masks and lithographic exposures. By dividing the single complex patterning task into sequential simpler steps, each operating at relaxed spacing requirements, the final result achieves tight spacing that would be impossible in a single lithographic step. The cut mask layer enables this multi-stage segmentation approach.
Solution Approach 2:
The patent performs preliminary actions by forming the combined diffusion contact region and cut mask layer structure before final patterning. These preparatory structures are created with larger, lithographically-resolvable dimensions, then subsequently processed to achieve the final tight spacing. The preliminary structures serve as templates that guide the formation of the final high-density pattern.
3Device complexity
If conventional photolithography is used to pattern features, then the manufacturing process is simple, but the minimum pitch between lines is limited by lens aperture and wavelength
Solution Approach 1:
The patent segments the single complex lithographic patterning operation into multiple simpler patterning steps, each with relaxed pitch requirements. The cut mask layer enables this segmentation by providing intermediate structures that guide subsequent patterning steps. This multi-step segmentation approach achieves sub-lithographic pitch while keeping each individual step within the capabilities of conventional photolithographic tools.
Solution Approach 2:
The cut mask layer serves as an intermediary structure between the combined diffusion contact region and the final patterned features. This intermediate layer enables the transfer of patterns at reduced spacing by acting as a template or mediator in the multi-step patterning process. The intermediary structure allows information to be transferred across scales, from lithographically-resolvable features to sub-lithographic final dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the placement of semiconductor device features closer together than previously possible, reducing the overall size of transistors and semiconductor devices, thereby achieving area optimization and improving manufacturing efficiency.
Implementation Method 1
an etch process may then be performed to remove an exposed third region within the combined region on the first layer of semiconductor material
Data Source
AI summary
Systems, apparatuses, and methods for reducing the area of a semiconductor structure. A spacing violation may be detected for a gap width used to separate first and second regions of a layer of semiconductor material. In response to detecting the violation, the first and second regions are merged into a combined region, and then a cut mask layer is formed above the combined region. Next, an etch process is performed through the cut mask layer to remove an exposed third region within the combined region, wherein the exposed third region is interposed between first and second region portions of the combined region.