Cut Metal Disposal for Inter-Wire Capacitance Reduction
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Solution Overview
Problem
In semiconductor integrated circuit design using multi-patterning techniques, the presence of unused branch wires leads to increased inter-wire capacitance and space errors due to the Miller effect, causing delays and power degradation.
Innovation Solution
A design aiding method that determines the optimal disposal number and positions of cut metals between adjacent cells based on branch wire lengths and types, minimizing adjacency between gate and drain wires to reduce parasitic capacitance and prevent space errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cut metals are disposed at both ends of each branch wire to prevent space errors, then manufacturing precision is improved, but inter-wire capacitance increases due to the Miller effect
Solution Approach 1:
The patent applies local quality by differentiating the treatment of branch wires based on their electrical characteristics. Only branch wires that are electrically connected to other wires (and thus subject to the Miller effect) have cut metals disposed at both ends, while other branch wires have cut metals disposed at only one end or not at all. This selective approach reduces unnecessary cut metals and minimizes inter-wire capacitance while still preventing space errors where needed.
2Loss of energy
If the number of cut metals is reduced to decrease inter-wire capacitance, then power consumption is improved, but space errors may occur between adjacent cells
Solution Approach 1:
The patent employs feedback by using the wire type information (whether a branch wire is electrically connected to other wires) to determine the optimal disposal strategy for cut metals. This feedback mechanism allows the system to automatically adjust the number and position of cut metals based on the electrical characteristics of each branch wire, ensuring space error prevention is maintained while minimizing inter-wire capacitance and power consumption.
3Manufacturing precision
If cut metals are disposed at both ends of branch wires, then space errors are prevented, but delays increase due to increased inter-wire capacitance from the Miller effect
Solution Approach 1:
The patent applies local quality by selectively applying the dual cut metal configuration only to branch wires that are electrically connected to other wires (gate, drain, or source wires). For branch wires that are not electrically connected, the patent uses a single cut metal or no cut metal, thereby avoiding unnecessary inter-wire capacitance and signal delays while still maintaining space error prevention where it is actually needed.
Data Source
AI summary
A computer-readable recording medium stores therein a design aiding program that aids layout design of a circuit under design and that is executable by a computer, the design aiding program includes: an instruction for disposing a plurality of cells in a layout of the circuit under design, based on circuit information related to the circuit under design; and an instruction for determining, for two adjacent cells of the cells disposed in the layout, a disposal number and disposal positions of cut metals to be disposed between the two adjacent cells, based on lengths of branch wires in each of the two adjacent cells and a type of a wire that includes the branch wires, each of the lengths being between a via and a cell frame of said each of the two adjacent cells, the via being on the wire in the two adjacent cells.