Cut-Metal-Gate Etching via Segmented Bias and Liner Protection
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Solution Overview
Problem
The semiconductor industry faces challenges in etching processes for small critical dimensions and high aspect ratios, leading to excessive loss of interlayer dielectric material, which can degrade device performance or cause failures.
Innovation Solution
The etching process is broken into multiple stages, with an initial etching process performed at a larger critical dimension and lower aspect ratio to minimize interlayer dielectric loss, followed by a second etching process with a higher bias to achieve the desired small critical dimension, using an extra liner layer to reduce excessive loss during the second etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single etching process is used to achieve small critical dimensions, then the desired small critical dimension is obtained, but excessive interlayer dielectric material is lost
Solution Approach 1:
The etching process is divided into multiple stages: a first etching process with lower bias to establish initial openings, followed by a second etching process with higher bias to achieve the final small critical dimension. This segmentation allows each stage to be optimized independently, preventing excessive interlayer dielectric loss while achieving the desired precision.
Solution Approach 2:
A liner layer is deposited before the second etching process to protect the interlayer dielectric material. This preliminary protective action ensures that when the higher bias second etching is performed, the interlayer dielectric loss is minimized while still achieving the required small critical dimension.
2Manufacturing precision
If etching bias is increased to achieve small critical dimensions, then the critical dimension is reduced, but interlayer dielectric loss increases
Solution Approach 1:
The etching process is segmented into two stages with different bias levels. The first stage uses lower bias etching to create initial openings without excessive interlayer dielectric loss. The second stage uses higher bias etching to achieve the final small critical dimension, but only after the liner layer is in place to protect against excessive loss.
Solution Approach 2:
The liner layer acts as an intermediary protective layer between the high bias etching process and the interlayer dielectric material. It allows the high bias etching to proceed effectively for achieving small critical dimensions while preventing excessive loss of the interlayer dielectric material.
3Loss of substance
If multiple etching stages are used to minimize interlayer dielectric loss, then material loss is reduced, but process complexity increases
Solution Approach 1:
The etching process is divided into two distinct stages with different bias settings, allowing each stage to be optimized for its specific purpose while managing overall process complexity through systematic organization.
Solution Approach 2:
The liner layer serves as a simple intermediary addition that enables the multi-stage process to function effectively. This single additional layer simplifies the coordination between the two etching stages by providing a consistent protective function throughout the process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents excessive interlayer dielectric loss while maintaining the required small critical dimension, ensuring reliable device performance by reducing the etching bias in the first stage and tolerating minor loss in the second stage.
Implementation Method 1
performing a first etching process to etch the opening partially into the first layer and partially into the ILD
Data Source
AI summary
A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.