Cut Metal Gate Isolation Structure for FinFET RC Delay Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased resistive-capacitive delay and oxidation issues that affect the integration density and threshold voltage of FinFETs, which existing technologies have not adequately addressed.
Innovation Solution
A cut metal gate (CMG) isolation structure is formed using multiple layers, including a silicon nitride layer as a barrier to prevent diffusion and a silicon layer that acts as a barrier to oxidation, reducing the dielectric constant and maintaining threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but resistive-capacitive delay increases
Solution Approach 1:
The gate structure is segmented into a metal gate portion and a cut portion, creating separate functional regions. The metal gate portion provides electrical functionality while the cut portion allows for isolation structure formation, enabling reduced resistive-capacitive delay while maintaining integration density
Solution Approach 2:
An intermediary isolation structure is introduced between adjacent FinFETs at the gate level. This isolation structure acts as a mediator to reduce parasitic capacitance and resistive-capacitive delay between closely spaced transistors, enabling higher integration density without compromising signal integrity
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but oxidation issues affect threshold voltage
Solution Approach 1:
An oxidation barrier layer is formed preliminarily on the gate structure before subsequent processing steps. This barrier layer prevents oxidation of the metal gate material, thereby maintaining stable threshold voltage characteristics even as feature sizes are reduced for higher integration density
Solution Approach 2:
The gate structure employs composite materials including a metal gate layer, an oxidation barrier layer, and a gate dielectric layer. This composite structure provides both the electrical functionality of the metal gate and protection against oxidation through the barrier layer, enabling reliable operation at reduced feature sizes
3Ease of manufacture
If a traditional gate structure is used, then manufacturing is simpler, but resistive-capacitive delay and oxidation issues cannot be adequately addressed
Solution Approach 1:
The gate structure is segmented into a metal gate portion and a cut portion, creating separate functional regions. The metal gate portion provides electrical functionality while the cut portion allows for isolation structure formation, enabling reduced resistive-capacitive delay while maintaining integration density
Solution Approach 2:
An intermediary isolation structure is introduced between adjacent FinFETs at the gate level. This isolation structure acts as a mediator to reduce parasitic capacitance and resistive-capacitive delay between closely spaced transistors, enabling higher integration density without compromising signal integrity
Solution Approach 3:
An oxidation barrier layer is formed preliminarily on the gate structure before subsequent processing steps. This barrier layer prevents oxidation of the metal gate material, thereby maintaining stable threshold voltage characteristics even as feature sizes are reduced for higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMG isolation structure improves resistive-capacitive delay without degrading threshold voltage, enabling better integration density and performance in FinFETs.
Implementation Method 1
the silicon layer acts as a barrier to oxidation of the underlying barrier layer and the gate stacks
Implementation Method 2
the silicon nitride layer acts as a barrier layer to prevent the diffusion of the materials of the gate stacks into the CMG trenches
Data Source
AI summary
An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.