Cut Metal Gate Layout for Tighter Endcap Spacing
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the constraint on lithographic processes due to the scaling of multi-gate and nanowire transistors, particularly in maintaining mobility and short channel control as dimensions approach the 10 nanometer node, leading to issues with gate endcap spacing and metal fill capability.
Innovation Solution
Implementing a 'plug-last' approach where the metal gate cut process occurs subsequent to gate dielectric and work function metal deposition, allowing for seamless work function metal deposition without voids and improving endcap spacing by eliminating the need for gate dielectric on the plug sidewalls, thus enhancing metal fill capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate fabrication process is used on bulk silicon substrates, then manufacturing cost is reduced and fabrication complexity is lowered, but gate endcap spacing is insufficient and metal fill capability deteriorates
Solution Approach 1:
The patent applies preliminary action by forming gate plugs with dielectric material and defining gate cuts before metal gate deposition. This sequence allows the metal fill process to occur in pre-defined spaces, ensuring proper endcap spacing is maintained while enabling seamless metal deposition without voids. The gate cut definition occurs at an earlier stage, preparing the structure for subsequent metal filling.
2Productivity
If feature dimensions are scaled down to maintain increased device density, then capacity is improved, but lithographic process constraints worsen and metal fill capability deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar gating to three-dimensional multi-gate structures (tri-gate and gate-all-around). This dimensional change allows the gate to wrap around the channel from multiple directions, providing superior electrostatic control and enabling continued scaling. The vertical dimension is exploited to maintain gate control over the channel as horizontal dimensions shrink, thereby managing lithographic constraints while preserving device performance.
3Device complexity
If gate dielectric is deposited on plug sidewalls in conventional processes, then gate structure is formed, but space constraints worsen and metal fill capability deteriorates due to void formation
Solution Approach 1:
The patent extracts the gate dielectric from the plug sidewall region by removing or not forming dielectric material on the vertical sidewalls of the gate plug. This creates clean, exposed sidewalls that allow metal to deposit seamlessly without forming voids. The dielectric is taken out from the critical metal fill region while still maintaining electrical isolation where needed, thereby enabling high-quality metal filling.
4Productivity
If endcap spacing is reduced to increase device density, then capacity is improved, but metal fill capability worsens and void formation increases
Solution Approach 1:
The patent introduces gate plugs made of dielectric material as intermediary structures that define the endcap regions. These plugs serve as spacers and templates that maintain precise endcap spacing while providing a foundation for seamless metal gate deposition. The dielectric plugs mediate between the requirement for tight spacing and the requirement for void-free metal filling, allowing both objectives to be achieved simultaneously.
Data Source
AI summary
Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.