Cut Metal Gate Plug Structure for FinFET RC Delay Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased resistive-capacitive delay and difficulty in maintaining threshold voltage without degrading the performance of fin field effect transistors (FinFETs) during manufacturing.
Innovation Solution
A cut metal gate (CMG) isolation structure is formed using multiple layers, including a silicon nitride layer as a barrier to prevent diffusion and a silicon layer that acts as a barrier to oxidation, reducing the dielectric constant and protecting underlying layers, thereby improving resistive-capacitive delay without degrading threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but resistive-capacitive delay increases and threshold voltage control becomes difficult
Solution Approach 1:
The gate structure is segmented into a metal gate portion and a cut metal gate isolation structure with multiple layers (silicon nitride barrier layer, silicon layer, and silicon oxide dielectric layer). This segmentation allows each layer to perform specific functions: the silicon nitride layer prevents diffusion, the silicon layer prevents oxidation, and the silicon oxide layer provides electrical isolation, collectively resolving the reliability issues associated with reduced feature sizes
Solution Approach 2:
The cut metal gate isolation structure uses a composite material system consisting of silicon nitride, silicon, and silicon oxide layers. Each material is selected for its specific properties: silicon nitride as a diffusion barrier, silicon as an oxidation barrier, and silicon oxide as a dielectric material. This composite structure enables simultaneous achievement of low resistive-capacitive delay and maintained threshold voltage control in scaled devices
2Ease of manufacture
If conventional isolation structures are used in scaled devices, then manufacturing is simpler, but threshold voltage degrades and resistive-capacitive delay increases
Solution Approach 1:
The silicon nitride barrier layer and silicon layer are formed preliminarily within the cut metal gate isolation structure before final device operation. These layers pre-establish diffusion and oxidation barriers that protect the underlying semiconductor structure throughout subsequent processing and device operation, preventing threshold voltage degradation and reducing resistive-capacitive delay without complicating the manufacturing flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CMG isolation structure effectively enhances resistive-capacitive delay while maintaining threshold voltage performance, allowing for improved integration density and device performance in FinFETs.
Implementation Method 1
the silicon nitride layer acts as a barrier layer to prevent the diffusion of the materials of the gate stacks into the CMG trenches during subsequent processing
Implementation Method 2
the silicon layer acts as a barrier to oxidation of the underlying barrier layer and the gate stacks
Implementation Method 3
a silicon oxide layer can be formed on the silicon layer, which reduces the dielectric constant of the CMG isolation structure
Data Source
AI summary
An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.