Cut Metal Gate Structure With Dielectric Plug for Void-Free Scaling
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors to smaller dimensions is exacerbated by constraints on lithographic processes, leading to issues with critical dimension and spacing, as well as challenges in maintaining mobility and short channel control, particularly in the fabrication of tri-gate transistors on bulk silicon substrates.
Innovation Solution
Implementing a 'plug-last' approach where the metal gate cut process is performed after gate dielectric and work function metal deposition, allowing for seamless work function metal deposition and reducing void formation by alleviating space constraints through the use of dielectric plugs with a dielectric liner and fill, which includes silicon, oxygen, and optionally carbon and halogen elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate and nanowire transistors are scaled to smaller dimensions to increase device density, then device capacity and integration density are improved, but lithographic process constraints worsen due to trade-offs between critical dimension and feature spacing
Solution Approach 1:
The gate structure is segmented into multiple components: a gate dielectric layer, a work function metal layer, and a conductive gate fill layer. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall scalability to smaller dimensions
Solution Approach 2:
The patent transitions from planar 2D transistors to three-dimensional multi-gate and nanowire structures. By adding vertical dimensionality with gates wrapping around channels from multiple sides, the invention achieves improved short channel control and density without being constrained by lithographic spacing limitations in the lateral plane
2Ease of manufacture
If tri-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing cost and process complexity are improved, but maintaining mobility improvement and short channel control at dimensions below 10nm becomes challenging
Solution Approach 1:
The channel structure uses composite materials including silicon-germanium (SiGe) sacrificial layers combined with silicon nanowire channels. This composite approach enables self-aligned gate wrapping while maintaining crystal quality and carrier mobility, achieving both ease of manufacture through bulk silicon compatibility and reliable short channel control at sub-10nm dimensions
3Device complexity
If metal gate cut process is performed before gate dielectric and work function metal deposition to improve fabrication sequence, then process simplicity is improved, but void formation and mis-registration issues worsen due to space constraints
Solution Approach 1:
The gate dielectric and work function metal layers are deposited preliminarily onto the channel structure before the metal gate cut is performed. This preliminary action establishes precise alignment references that guide subsequent gate patterning, eliminating mis-registration issues while maintaining a straightforward fabrication sequence
Solution Approach 2:
The gate dielectric layer serves as an intermediary between the channel structure and the metal gate fill. This intermediary layer provides a stable foundation that prevents void formation during metal deposition and ensures uniform work function metal coverage, resolving both void formation and alignment precision issues
Data Source
AI summary
An integrated circuit structure includes a fin or a plurality of horizontally stacked nanowires above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the fin or the plurality of horizontally stacked nanowires and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin or the plurality of horizontally stacked nanowires, the dielectric gate plug including a dielectric liner including silicon and oxygen, and a dielectric fill including silicon and oxygen, with a seam between the dielectric liner and the dielectric fill. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.