Cut Metal Gate Structure With Dielectric Plugs for Tight IC Spacing
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors is exacerbated by constraints on lithographic processes, leading to issues with critical dimension and spacing, which affect the performance and reliability of integrated circuits, particularly in the fabrication of tri-gate transistors on bulk silicon substrates.
Innovation Solution
Implementing a 'plug-last' approach where the metal gate cut process is performed after gate dielectric and work function metal deposition, allowing for seamless work function metal deposition and reducing the need for additional space for metal fill, thereby alleviating space constraints and improving yield by using dielectric plugs with specific compositions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multi-gate transistor fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and fabrication complexity is lowered, but critical dimension control and spacing constraints deteriorate
Solution Approach 1:
The gate structure is segmented into multiple components: a gate dielectric layer, a work function metal layer, and a metal fill layer. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall manufacturing simplicity. The gate is also divided into active regions and endcap regions, with the endcap portions selectively removed to improve spacing control.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional multi-gate structures (such as tri-gate or gate-all-around configurations). This dimensional change enables improved critical dimension control and spacing management by utilizing vertical stacking and lateral positioning in multiple dimensions, thereby resolving the contradiction between manufacturing simplicity and precision.
2Productivity
If feature dimensions are scaled down to increase device density, then capacity increases, but lithographic process constraints worsen
Solution Approach 1:
By transitioning to multi-gate and nanowire structures that extend into the vertical dimension, the patent achieves higher device density without proportionally increasing lithographic complexity. The vertical stacking allows more functional units to be packed into the same planar footprint, effectively bypassing some lithographic limitations.
Solution Approach 2:
The gate structure employs nested layers where the gate dielectric is surrounded by the work function metal, which is in turn surrounded by the metal fill layer. This nested configuration maximizes functional integration within minimal lateral space, increasing device density while maintaining manageable lithographic requirements.
3Area of stationary object
If metal gate cut is performed before gate dielectric deposition, then additional space for metal fill is available, but work function metal deposition becomes discontinuous and complex
Solution Approach 1:
The patent inverts the conventional sequence by performing metal gate cut after gate dielectric and work function metal deposition. This reversal allows the work function metal to be deposited continuously over the entire gate region including endcaps, simplifying the deposition process. The metal fill is then selectively removed from endcap regions to create the necessary spacing.
Solution Approach 2:
The gate dielectric and work function metal layers are deposited in advance before the metal gate cut operation. This preliminary action ensures continuous, simplified deposition processes while still allowing subsequent selective removal of metal fill from endcap regions to achieve the required spacing and positioning.
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
An integrated circuit structure includes a fin or a plurality of horizontally stacked nanowires above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the fin or the plurality of horizontally stacked nanowires and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin or the plurality of horizontally stacked nanowires, the dielectric gate plug including a dielectric liner including silicon and oxygen, and a dielectric fill including silicon and oxygen, with a seam between the dielectric liner and the dielectric fill. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.