Cut Metal Gate Layout for Tighter Fin Spacing in SRAM

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to reduce spacing between semiconductor fins while maintaining large epitaxial source/drain features to avoid short defects and reduce contact resistance, which is crucial for enhancing device integration and performance.

Innovation Solution

A cut metal gate process is employed, involving two exposure and two etching steps (2P2E) to separate merged epitaxial S/D features and cut metal gates, allowing for closer fin spacing and larger S/D features, thereby improving device integration and reducing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If large epitaxial source/drain features are formed to reduce contact resistance, then contact resistance is reduced, but spacing requirements among devices increase, reducing device integration

Engineering Contradiction:
Improvecontact resistanceVSAvoiddevice integration
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies segmentation by dividing the gate structure into separate segments using cut metal gates. This allows adjacent fins to be positioned closer together while maintaining sufficiently large epitaxial source/drain features for low contact resistance. The gate is segmented into multiple gates (e.g., first gate and second gate) separated by gate trenches, enabling independent optimization of each transistor's source/drain region size without requiring increased spacing between adjacent devices.

Inventive Principle:
Principle #1Segmentation

2Productivity

If spacing among devices is reduced to increase integration, then device integration is improved, but epitaxial source/drain features may merge, causing short defects

Engineering Contradiction:
Improvedevice integrationVSAvoidshort defects
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cut metal gate process segments the gate into separate gates for adjacent fins, with gate trenches positioned between them. This segmentation allows the epitaxial source/drain features to grow larger and merge for low contact resistance while the gate trenches prevent electrical shorting between adjacent devices. The segmentation creates physical and electrical isolation between neighboring transistors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate trench acts as an intermediary structure between adjacent fins and their epitaxial source/drain features. This intermediary element allows the source/drain features to extend and merge for reduced contact resistance while the trench provides electrical isolation to prevent short defects. The intermediary structure enables both features to coexist without conflict.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional gate processes are used, then manufacturing is simpler, but fin spacing must be larger to prevent epitaxial feature merging

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidfin spacing
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent implements segmentation of the gate structure into multiple separate gates with gate trenches between them. This segmentation enables closer fin spacing while maintaining sufficiently large epitaxial source/drain features. The process involves forming a continuous gate structure first, then selectively removing portions to create segments, which allows better control over spacing and source/drain feature sizes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by forming the complete gate structure before segmenting it. The gate is initially formed as a continuous structure covering multiple fins, then specific portions are removed to create the segmented structure. This preliminary formation simplifies the manufacturing process compared to forming separate gates individually, while still achieving the benefits of reduced fin spacing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250308882A1Cut metal gate process for reducing transistor spacing
Publication Date: 2025.10.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250308882A1 patent drawing
  • US20250308882A1 patent drawing
  • US20250308882A1 patent drawing

AI summary

A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.