Cut Metal Gate Dielectric Removal for Uniform FinFET Threshold Voltage
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Solution Overview
Problem
The complexity of processing and manufacturing FinFETs is increased due to the need for precise removal of dielectric layers during the cut-metal-gate process, leading to non-uniformity in threshold voltage and trench width, which affects transistor performance.
Innovation Solution
A method is developed to uniformly remove dielectric layers by adjusting process conditions such as temperature distribution, pressure, and flow rate of dilute gases, ensuring consistent removal across the wafer surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dielectric removal methods are used during cut-metal-gate process, then the process can be completed, but non-uniformity in threshold voltage and trench width occurs
Solution Approach 1:
The patent applies parameter changes by systematically adjusting temperature distribution, pressure, and gas flow rate during the dielectric removal process. Specifically, the temperature is controlled to be lower at the wafer center than at the edges, pressure is maintained between 20-100 mTorr, and gas flow rates are optimized to achieve uniform etching across the wafer surface, thereby resolving the non-uniformity issue without increasing process complexity
2Reliability
If dielectric layers are removed during cut-metal-gate process, then trench formation is achieved, but voltage shifts occur affecting transistor performance
Solution Approach 1:
The patent implements feedback control by continuously monitoring and adjusting process parameters based on their effect on dielectric removal uniformity. The temperature distribution is actively controlled to compensate for natural thermal gradients, and gas flow rates are adjusted based on etching rate measurements, thereby minimizing voltage shifts and improving transistor performance consistency
3Productivity
If standard etching conditions are used, then dielectric removal proceeds, but non-uniform removal across wafer surface occurs
Solution Approach 1:
The patent applies local quality by implementing spatially varying process conditions across the wafer surface. Different regions of the wafer receive different temperature conditions (cooler center, warmer edges) and adjusted gas flow rates to compensate for natural variations in heat transfer and gas distribution, thereby achieving uniform dielectric removal across the entire wafer surface while maintaining high productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the uniformity of threshold voltage and trench width, reducing voltage shifts by up to 30 mV and enhancing the overall performance of FinFETs.
Implementation Method 1
reacting the second portion of the dielectric layer with HF and ammonia to form a solid layer
Implementation Method 2
heating the solid layer to sublimate the solid layer, so that sidewalls of the conductive region are exposed
Data Source
AI summary
A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.