Cutting Insert Groove Design for Chip Discharge
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Solution Overview
Problem
The concave groove with a flat bottom surface in cutting inserts can lead to jammed chips due to enhanced hardness, resulting in poor chip discharge performance.
Innovation Solution
The cutting insert design features a concave groove with a first bottom surface continuous with the cutting edge and a second bottom surface located at a lower position, along with inclined surfaces that curl chips into a space below the virtual extension line of the first bottom surface, reducing curl diameter and stabilizing chip discharge direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If chips are compressed in the width direction by the concave groove, then the width of chips becomes smaller and they are less likely to contact the machined surface, but the enhanced hardness of compressed chips makes them less likely to be divided by the inclined surface, causing chips to be jammed in the concave groove
Solution Approach 1:
The patent transitions from a two-dimensional flat bottom surface to a three-dimensional stepped bottom surface structure with first and second bottom surfaces at different heights. This dimensional change creates additional space for chip accumulation and allows chips to be curled into a space below the virtual extension line of the first bottom surface, preventing jamming while maintaining compressed chip width for protected machined surfaces.
Solution Approach 2:
The patent introduces curved inclined surfaces that curl the compressed chips into a spiral or curved path, reducing the curl diameter and directing chips into the space created by the stepped bottom surface. This curvature transformation helps hard, compressed chips change direction smoothly without jamming in the concave groove.
2Device complexity
If a flat bottom surface is used in the concave groove, then the structure is simple, but chips become jammed tight due to enhanced hardness, deteriorating chip discharge performance
Solution Approach 1:
The patent segments the previously uniform flat bottom surface into two distinct levels: a first bottom surface continuous with the cutting edge and a second bottom surface at a lower position. This segmentation creates additional space for chip accommodation and prevents jamming of hard chips, improving chip discharge performance while adding only moderate structural complexity.
3Object-affected harmful factors
If chips are compressed to reduce width, then contact with machined surface is reduced, but chip discharge becomes unstable due to jamming in the concave groove
Solution Approach 1:
The stepped bottom surface structure acts as an intermediary element between the compressed chips and the concave groove walls. The second bottom surface at a lower position provides a transition zone that prevents direct contact between hard, compressed chips and the groove boundaries, reducing jamming and stabilizing chip discharge while maintaining the compressed chip configuration for protected machined surfaces.
Data Source
Figure 1(a)~1(c)
Figure 2(a)~2(c)
Figure 3(a)~3(c)
AI summary
A cutting insert having excellent chip discharge performance is provided. In the cutting insert of the present invention, a bottom surface of a concave groove 21 includes a first bottom surface 211 continuous with a cutting edge part 5, and a second bottom surface 212 which is located on a side further remote from the cutting edge part 5 than the first bottom surface 211, and is located at a lower position than a virtual extension line L1 of an end portion of the first bottom surface 211 on a side remote from the cutting edge part 5. Further, a pair of inclined surfaces 23 are located on a side further remote from the cutting edge part 5 than the end portion of the first bottom surface 211 on the side remote from the cutting edge part 5 in a top view. Therefore, the diameter of generated chips decreases by the fact that the chips are curled while sinking in space formed at a lower position than the virtual extension line L1 of the first bottom surface 211. Consequently, the chip discharge direction is stabilized, thus achieving satisfactory chip discharge performance.