CVD Interfacial Dielectric for Ohmic Contact Resistance
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Solution Overview
Problem
As semiconductor devices scale smaller, direct metal-to-semiconductor contacts become highly resistive, leading to increased complexity and cost in forming silicide or germanide layers to reduce Schottky barrier height, and there is a need for a method to decrease contact resistance without Fermi level pinning.
Innovation Solution
Depositing a thin interfacial dielectric layer with a thickness between 3 Å and 20 Å, made of materials like titanium oxide or zinc oxide, between the metal and semiconductor to unpin the metal Fermi level, thereby reducing Schottky barrier height and contact resistance, eliminating the need for silicide or germanide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If direct metal-to-semiconductor contact is used, then device scaling is simplified, but contact resistance becomes highly resistive
Solution Approach 1:
An interfacial dielectric layer is introduced between the metal contact and semiconductor substrate to serve as an intermediary that unpins the metal Fermi level from the semiconductor. This dielectric layer with specific thickness (3-20 Å) and material composition (e.g., titanium oxide, zinc oxide) enables tuning of the Schottky barrier height while maintaining ohmic contact characteristics, thereby reducing contact resistance without requiring direct metal-to-semiconductor contact
Solution Approach 2:
The Schottky barrier height is tuned by changing parameters of the interfacial dielectric layer, including its thickness (3-20 Å), material composition (titanium oxide, strontium titanium oxide, zinc oxide, tantalum oxide, lanthanum oxide, zinc sulfide, zinc selenide, germanium oxide, cadmium oxide, or tin oxide), and energy bandgap (>2.0 eV). These parameter changes enable optimization of contact resistance while maintaining device scalability
2Reliability
If silicide or germanide layers are deposited to reduce Schottky barrier height, then contact resistance decreases, but processing complexity and cost increase
Solution Approach 1:
The complex multi-step silicide or germanide formation process is replaced by a single interfacial dielectric deposition step. The patent extracts the essential function of reducing Schottky barrier height from the complex silicide/germanide process and achieves it through a simpler dielectric layer deposition, thereby reducing processing complexity and cost while maintaining low contact resistance
Solution Approach 2:
Instead of changing material composition through silicide or germanide formation, the patent achieves Schottky barrier height reduction by changing parameters of the interfacial dielectric layer (thickness, material composition, energy bandgap). This parameter-based approach simplifies processing while achieving the desired electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases contact resistance, simplifies processing, and optimizes transistor performance by tuning the Schottky barrier height without introducing additional processing steps or strain on the semiconductor device.
Implementation Method 1
the interfacial dielectric is configured to unpin the metal Fermi level from the source or drain regions of the substrate
Implementation Method 2
depositing by chemical vapor deposition (CVD) an interfacial dielectric over the source and drain regions of the substrate
Data Source
AI summary
An apparatus and method for manufacturing an interconnect structure to provide ohmic contact in a semiconductor device is provided. The method includes providing a semiconductor device, such as a transistor, comprising a substrate, a gate dielectric, a gate electrode, and source and drain regions in the substrate. An ultra-thin interfacial dielectric is deposited by chemical vapor deposition (CVD) over the source and drain regions, where the interfacial dielectric can have a thickness between about 3 Å and about 20 Å. The ultra-thin interfacial dielectric is configured to unpin the metal Fermi level from the source and drain regions. Other steps such as the deposition of a metal by CVD and the cleaning of the substrate surface can be performed in an integrated process tool without a vacuum break. The method further includes forming one or more vias through a pre-metal dielectric over the source and drain regions of the substrate.