Memory Tiering Using CXL Access Logs to Reduce NUMA Scan Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory tiering systems face challenges with high latency due to non-uniform memory access (NUMA) balancing scans, which cause CPU resource wastage, page faults, and unpredictable access sequences, leading to suboptimal system performance.
Innovation Solution
The proposed systems and methods utilize cache coherent protocols like CXL to avoid NUMA balancing scans by using access logs and CXL device capability hints to migrate pages between memory tiers based on access counters, ensuring efficient promotion and demotion of pages without CPU overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NUMA balancing scans are used for memory tiering, then memory pages can be distributed across memory nodes, but CPU resources are wasted and latency increases
Solution Approach 1:
The patent extracts the NUMA balancing scan function from the memory tiering system by using access logs maintained by the CXL device itself. The device autonomously tracks access patterns and provides this information to the host, eliminating the need for CPU-based scanning while preserving memory distribution capabilities
Solution Approach 2:
The CXL device performs self-service by maintaining its own access logs and autonomously tracking page access patterns. This self-monitoring capability removes the burden of access pattern detection from the host CPU, reducing latency while maintaining adaptability
2Measurement precision
If NUMA balancing scans are performed, then memory access patterns can be tracked, but page faults occur and CPU overhead increases
Solution Approach 1:
The access log acts as an intermediary between the CXL device and the host memory management system. The device maintains detailed access pattern information in its own logs, providing this data to the host only when needed, thus achieving precise tracking without continuous CPU intervention
Solution Approach 2:
The CXL device performs preliminary action by pre-tracking and recording access patterns in its internal logs before the host needs this information. This advance preparation eliminates the need for reactive scanning and page faults, improving CPU efficiency while maintaining measurement precision
3Productivity
If traditional memory tiering is used, then pages can be migrated between tiers, but access sequences become unpredictable
Solution Approach 1:
The system implements feedback by using access log information to guide page migration decisions. The host queries the device's access logs to determine which pages have been accessed recently or frequently, ensuring that migration decisions are based on actual access patterns rather than predictions, thus maintaining predictability
Data Source
AI summary
Provided are systems, methods, and apparatuses for systems and methods for reducing latency of memory tiering devices. In one or more examples, the systems, devices, and methods include determining a number of pages in a first memory tier satisfies a threshold; based on the number of pages in the first memory tier satisfying the threshold, obtaining from an access log an access counter and a first physical address associated with a page of a second memory tier; translating the first physical address to a second physical address associated with a host; and modifying, based on the access counter, a counter field of a first data structure.