CXL Tagged Capacity Migration to NVMe Namespaces

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Solution Overview

Problem

Existing memory systems lack flexibility in managing tagged capacity units, as the allocation and migration of data between compute express link (CXL) and nonvolatile memory express (NVMe) devices is inefficient, limiting compatibility and resource utilization.

Innovation Solution

Implementing migrate commands that enable data migration between tagged capacity units in CXL memory devices and NVMe namespaces, allowing for dynamic allocation and reallocation of memory resources while maintaining tag and namespace compatibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is stored in tagged capacity units of CXL memory devices, then fast access and flexibility are improved, but resource utilization and compatibility with other memory devices deteriorate

Engineering Contradiction:
Improvedata access speedVSAvoidcompatibility with NVMe devices
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent implements migrate commands that enable tagged capacity units in CXL memory devices to be migrated to NVMe namespaces, allowing the same data structure to be accessed by both CXL and NVMe protocols. This multi-functionality resolves the contradiction by maintaining fast access through CXL while enabling compatibility with NVMe devices through migration capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic migration capabilities where data can be moved between CXL tagged capacity units and NVMe namespaces based on workload requirements. This dynamic approach allows the system to switch between fast CXL access and compatible NVMe access, resolving the contradiction between speed and adaptability.

Inventive Principle:
Principle #15Dynamics

2Ease of operation

If memory resources are statically allocated in CXL devices, then management simplicity is improved, but resource utilization efficiency deteriorates

Engineering Contradiction:
Improvememory management simplicityVSAvoidresource utilization efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements dynamic migration commands that allow memory resources to be reallocated between CXL tagged capacity units and NVMe namespaces based on actual workload demands. This transforms static allocation into dynamic allocation, improving resource utilization while maintaining manageable complexity through standardized commands.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The migration mechanism creates logical copies of data between CXL and NVMe interfaces, allowing the same physical data to be accessed through different protocols. This copying approach enables flexible resource allocation without requiring complex physical reconfiguration, balancing simplicity and efficiency.

Inventive Principle:
Principle #26Copying

3Reliability

If separate memory devices are used for CXL and NVMe protocols, then protocol performance is improved, but system complexity and resource allocation overhead increase

Engineering Contradiction:
Improveprotocol performanceVSAvoidsystem architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges CXL tagged capacity unit functionality with NVMe namespace functionality through a unified migration command structure. This allows separate protocol optimizations to be maintained while reducing system complexity by enabling shared resource management between the two protocols.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250377818A1Migrate command associated with tagged capacity in a compute express link (CXL) memory device coupled with a nonvolatile memory express (NVME) memory device
Publication Date: 2025.12.11 MICRON TECHNOLOGY INC
  • US20250377818A1 patent drawing
  • US20250377818A1 patent drawing
  • US20250377818A1 patent drawing

AI summary

A system can include a first memory device comprising a plurality of dynamic capacity devices, a second memory device, and a processing device, operatively coupled with the first and second memory devices. The processing device is configured to perform operations including receiving a host command to move first data associated with a first tag to the second memory device, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data; responsive to receiving the host command to move, determining a second memory section of the second memory device, wherein the second memory section is associated with a namespace of the second memory device; and storing the first data in the second memory section associated with the namespace.