Direct Storage Buffer Architecture for CXL Accelerator Access
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Solution Overview
Problem
Existing storage systems face inefficiencies in supporting direct storage functions, particularly when accelerators like GPUs offload tasks from the host CPU, as they require using system buffer memory, leading to degraded system performance.
Innovation Solution
A storage device and system design with a multi-port and multi-physical function structure, utilizing a CXL protocol, allows accelerators to directly access the storage device through internal buffer memory without relying on external system buffer memory, enabling direct storage functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If accelerators use system buffer memory for direct storage access, then data storage capacity is available, but system performance degrades due to buffer memory dependency
Solution Approach 1:
The patent extracts the buffer memory dependency from the direct storage access path by implementing a buffer memoryless architecture. The storage device and accelerator can directly access each other's memory spaces without requiring external buffer memory, eliminating the performance degradation caused by buffer memory operations while maintaining reliable direct storage functionality.
2Quantity of substance
If external buffer memory is used for accelerator-accessed storage, then data temporarily storage is enabled, but latency increases and processing efficiency decreases
Solution Approach 1:
The patent merges the storage and processing functions by enabling the accelerator to directly access the storage device's memory space and vice versa. This consolidation eliminates the need for separate external buffer memory, reducing access latency while maintaining adequate temporary storage capacity through the integrated memory spaces of the storage device and accelerator.
3Adaptability or versatility
If multi-port structure with CXL protocol is implemented, then direct accelerator access is enabled, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the storage device and accelerator with universal memory access capabilities through CXL protocol. The same memory space can be accessed by both the host CPU and accelerators, and the same interface structure supports both traditional and direct storage modes, reducing overall system complexity despite the multi-port capability.
Data Source
AI summary
A storage device includes one or more ports that form an electrical connection with an external device, one or more physical functions including physical resources, and exposed through the one or more ports to communicate with the external device, a storage controller that controls an operation of the storage device, and communicates with the external device through the one or more ports and the one or more physical functions, nonvolatile memories controlled by the storage controller, and a first buffer memory controlled by the storage controller. When the storage device is accessed by the external device, the first buffer memory is used by the one or more ports and the one or more physical functions to temporarily store data for the external device.