CXL Dynamic Memory Expansion Without Power Cycling
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Solution Overview
Problem
Current DDR interface-based memory expansion in high-performance computing and futuristic data center environments is limited by its inability to provide dynamic memory expansion without requiring a power cycle, which hampers the ability to handle large-scale memory resource pools needed for AI, big data analytics, and other workloads.
Innovation Solution
The implementation of a Compute Express Link (CXL) interface enables dynamic memory capacity expansion without power cycling, allowing for modular, flexible, and composable memory and storage pooling solutions that can scale up or out while maintaining an active power state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DDR interface-based memory expansion is used, then memory capacity can be increased, but dynamic expansion capability is lost due to power cycle requirement
Solution Approach 1:
The patent introduces a CXL interface as an intermediary between the host system and memory pooling devices. This intermediary enables dynamic memory expansion by providing a communication protocol that allows memory capacity to be adjusted without power cycling the system, thus resolving the contradiction between memory expansion capability and power cycle requirement
Solution Approach 2:
The patent implements dynamic memory expansion capability through the CXL interface, allowing memory capacity to be changed while the system remains powered on. This transforms the static memory configuration (requiring power cycle) into a dynamic one (no power cycle needed), directly addressing the technical contradiction
2Adaptability or versatility
If CXL interface is introduced for memory expansion, then dynamic capacity expansion is enabled, but effective memory pooling solution is not yet achieved
Solution Approach 1:
The patent segments the memory system into host systems and memory pooling devices connected via CXL interface. This segmentation allows independent management and expansion of memory resources, enabling dynamic capacity expansion while simplifying the overall memory pooling solution through modular architecture
Solution Approach 2:
The patent creates a universal memory pooling solution based on CXL interface that can serve multiple host systems and support various memory expansion scenarios. This multi-functional approach resolves the complexity issue by providing a standardized, reusable architecture for memory pooling
3Ease of operation
If DDR interface is used for memory expansion, then system simplicity is maintained, but dynamic expansion capability is limited
Solution Approach 1:
The CXL interface acts as an intermediary that maintains ease of operation while enabling dynamic expansion capability. It provides a standardized protocol that simplifies the expansion process while simultaneously unlocking dynamic capacity adjustment, thus resolving the contradiction between operational simplicity and expansion adaptability
Data Source
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AI summary
Disclosed is a device including a host, a processor, a memory pooling device electrically connected to the processor, and a compute express link (CXL) dynamic memory capacity expansion device (DMCED), wherein the CXL DMCED is directly electrically connected to the memory pooling device and at least one of a memory capacity or a storage capacity in the memory pooling device is configured to be increased and decreased while maintaining an active power state of the device.