CXL Memory Coherence Across Edge Nodes With Selective Snooping
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Solution Overview
Problem
Existing Edge computing networks face high latency due to the use of two-phase commit protocols for data transactions between Edge compute nodes, which can rival the time it would take to communicate directly with a cloud server, and implementing cache coherence without these protocols results in inefficient bandwidth consumption.
Innovation Solution
Implementing the Compute Express Link (CXL) standard to establish cache coherency between multiple servers across a distributed Edge network using CXL.io, CXL.cache, and CXL.mem protocols, along with snooping techniques to manage cache coherence, reducing latency and bandwidth consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-phase commit protocols are used for data transactions between Edge compute nodes, then data consistency is ensured, but latency increases to levels comparable to cloud server communication
Solution Approach 1:
The patent introduces a distributed cache coherence system as an intermediary mechanism between Edge compute nodes. Instead of using two-phase commit protocols for every data transaction, the system employs cache coherence protocols (such as MESI, MOESI, or MESIF) that act as intermediaries to manage data consistency. This intermediary layer enables direct peer-to-peer data sharing between caches while maintaining consistency, thereby reducing latency compared to cloud server communication while preserving data reliability through coordinated cache invalidation and update mechanisms.
Solution Approach 2:
The patent segments the memory system into distributed cache domains across multiple Edge compute nodes. Each node maintains its own cache coherence state independently, allowing local data transactions to proceed without involving the entire distributed system. This segmentation enables fine-grained control over data consistency, where only relevant cache lines are invalidated or updated, rather than requiring global two-phase commit protocols for all transactions, thus reducing overall system latency while maintaining data integrity.
2Loss of time
If cache coherence is implemented without two-phase commit protocols, then latency is reduced, but bandwidth consumption becomes inefficient
Solution Approach 1:
The patent implements selective cache coherence where different coherence policies are applied to different memory domains or cache lines based on their access patterns and importance. Critical data that requires strong consistency maintains stricter coherence protocols, while less critical data uses more relaxed policies. This local differentiation optimizes bandwidth consumption by applying coherence overhead only where necessary, reducing overall energy loss while maintaining low latency for time-sensitive operations through localized coherence management rather than system-wide protocols.
Solution Approach 2:
The patent employs partial cache coherence where not all cache lines require full coherence validation. Instead of implementing exhaustive coherence checking for every memory access, the system applies coherence protocols selectively to specific cache domains or data types. This partial action approach reduces bandwidth consumption by avoiding unnecessary coherence traffic for data that doesn't require strict consistency, while still providing low-latency access for critical operations that do need coherence guarantees.
Data Source
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AI summary
Methods, apparatus, systems, and articles of manufacture are disclosed that reduce latency and bandwidth consumption when sharing memory across a distributed coherent Edge computing system. The distributed coherent Edge computing system disclosed herein configures a compute express link (CXL) endpoint to share data between memories across an Edge platform. The CXL endpoint configures coherent memory domain(s) of memory addresses, which are initialized from an Edge device connected to the Edge platform. The CXL endpoint also configures coherency rule(s) for the coherent memory domain(s). The CXL endpoint is implemented to snoop the Edge platform in response to read and write requests from the Edge device. The CXL endpoint selectively snoops memory addresses within the coherent memory domain(s) that are defined as coherent based on the coherency rule(s).