CXL Endpoint Memory Sharing for Low-Latency Edge Computing

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Solution Overview

Problem

Existing Edge computing networks face high latency due to the use of two-phase commit protocols for data sharing between Edge compute nodes, which can rival the latency of direct cloud communication, and cache coherence protocols are inefficient, leading to excessive bandwidth consumption and latency.

Innovation Solution

Implementing the Compute Express Link (CXL) standard to establish cache coherency between Edge compute nodes using CXL.io, CXL.cache, and CXL.mem protocols, enabling selective snooping and configuration of coherent memory domains and coherency rules to reduce latency and bandwidth consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If two-phase commit protocols are used for data sharing between Edge compute nodes, then data consistency is ensured, but latency increases to levels comparable to direct cloud communication

Engineering Contradiction:
Improvedata consistencyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the data sharing process into coherent memory domains with selective coherence, allowing only specific memory regions to participate in coherence protocols rather than all data. This reduces the scope of handshakes and latency while maintaining consistency for critical data.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically configures coherent memory domains and coherency rules based on workload requirements. Not all memory accesses require full coherence protocols - the system adapts the level of coherence enforcement to match actual needs, reducing unnecessary latency.

Inventive Principle:
Principle #15Dynamics

2Reliability

If cache coherence protocols are implemented for data sharing, then data consistency is maintained, but bandwidth consumption increases excessively

Engineering Contradiction:
Improvedata consistencyVSAvoidbandwidth consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies cache coherence selectively to specific memory domains rather than uniformly across all memory. By identifying which memory regions require coherence and configuring coherent memory domains accordingly, the system reduces bandwidth consumption while maintaining consistency where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Instead of implementing full cache coherence for all data, the system applies partial coherence only to necessary memory regions. This partial action approach reduces bandwidth consumption significantly while maintaining data consistency for the critical portions that require it.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If continuous handshakes are performed for data sharing between Edge nodes, then data consistency is ensured, but latency and bandwidth consumption increase

Engineering Contradiction:
Improvedata consistencyVSAvoiddata sharing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the continuous handshake requirement by implementing event-driven coherence notifications. Instead of continuous handshakes, coherence updates are triggered only when actual data changes occur in coherent memory domains, eliminating unnecessary communication overhead.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system replaces continuous handshakes with periodic or event-triggered coherence updates. Coherence protocols are activated only when needed (on data changes) rather than continuously, improving data sharing efficiency while maintaining consistency.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12445524B2Methods and apparatus to share memory across distributed coherent edge computing system
Publication Date: 2025.10.14 INTEL CORP
  • US12445524B2 patent drawing
  • US12445524B2 patent drawing
  • US12445524B2 patent drawing

AI summary

Methods, apparatus, systems, and articles of manufacture are disclosed that reduce latency and bandwidth consumption when sharing memory across a distributed coherent Edge computing system. The distributed coherent Edge computing system disclosed herein configures a compute express link (CXL) endpoint to share data between memories across an Edge platform. The CXL endpoint configures coherent memory domain(s) of memory addresses, which are initialized from an Edge device connected to the Edge platform. The CXL endpoint also configures coherency rule(s) for the coherent memory domain(s). The CXL endpoint is implemented to snoop the Edge platform in response to read and write requests from the Edge device. The CXL endpoint selectively snoops memory addresses within the coherent memory domain(s) that are defined as coherent based on the coherency rule(s).