CXL HBM Interface Core for Single-Step Protocol Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face increased latency due to the need for multiple protocol and interface conversions, such as those adhering to the JEDEC standard, which are performed twice, leading to inefficiencies in communication.
Innovation Solution
Implementing a Compute Express Link (CXL) memory device with an HBM interface core that directly converts data transmission to the DFI protocol, bypassing the need for JEDEC interface conversion, thereby reducing the number of conversion steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple protocol and interface conversions are performed according to JEDEC standard, then compatibility with existing memory systems is improved, but latency increases and communication efficiency deteriorates
Solution Approach 1:
The patent extracts and removes the intermediate JEDEC interface conversion layer from the data transmission path. By implementing a direct interface between the HBM interface core and the DFI protocol, the patent eliminates unnecessary conversion steps while maintaining compatibility with existing memory systems through selective implementation of only the essential protocol elements.
Solution Approach 2:
The patent introduces a simplified intermediary layer that directly maps HBM interface protocols to DFI protocol without requiring full JEDEC standard compliance. This intermediary enables direct communication between high-bandwidth memory and dual-precision floating-point arithmetic units, reducing latency while maintaining sufficient compatibility for the specific application domain.
2Adaptability or versatility
If multiple protocol conversions are performed, then broader system compatibility is achieved, but communication efficiency and performance deteriorate
Solution Approach 1:
The patent extracts only the essential protocol conversion functions needed for HBM-to-DFI communication, removing the redundant JEDEC standard compliance layers. This selective extraction maintains compatibility with the specific target system while eliminating performance-detrimental conversion steps.
Solution Approach 2:
Instead of converting HBM protocol through JEDEC standard to DFI (traditional path), the patent inverts the approach by implementing a direct HBM-to-DFI mapping that bypasses the intermediate JEDEC layer entirely, achieving both efficiency and targeted compatibility.
3Reliability
If JEDEC interface conversion is performed twice, then standard compliance is improved, but device complexity and latency increase
Solution Approach 1:
The patent removes one instance of JEDEC interface conversion from the data path, retaining only the essential compliance elements needed for reliable operation. This reduces the conversion process from two separate JEDEC compliance stages to a single streamlined implementation.
Solution Approach 2:
The patent merges multiple protocol conversion functions into a single integrated HBM interface core that directly handles HBM-to-DFI translation. This consolidation eliminates the need for separate conversion stages while maintaining necessary standard compliance for reliable system operation.
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A compute express link (CXL) memory device may include a high bandwidth memory (HBM) comprising a CXL base die and a plurality of core dies that are sequentially stacked on the CXL base die. The CXL base die may include an HMB interface intellectual property (IP) core configured to convert data transmission and reception between the plurality of core dies and dynamic random access memory (DRAM) in compliance with a CXL specification, and the HMB interface IP core corresponds to a non-Joint Electron Device Engineering Council (JEDEC) standard.