CXL I/O Scheduling With Query-Plan Status Synchronization

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Solution Overview

Problem

Existing I/O scheduling methods in host devices face delays due to long data loading times, leading to bottlenecks and inefficient resource management, particularly when multiple devices are connected through a CXL protocol.

Innovation Solution

Implementing a device with a device memory that stores synchronized query plan status information and a device processor to manage tasks efficiently, and a host device with a host memory that synchronizes query plan status information to optimize I/O scheduling by predicting task delays and parallel processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the host device waits for data loading completion before proceeding to the next stage, then data processing accuracy is ensured, but command execution time increases and productivity decreases

Engineering Contradiction:
Improvedata processing accuracyVSAvoidcommand execution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by having the device processor proactively detect task delay risks before they occur, and the host processor preemptively adjust scheduling decisions based on predicted completion times. This allows the system to maintain accurate data processing while avoiding unnecessary waiting, as the host can prepare next-stage commands in advance based on predicted device completion times.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the host device issues frequent I/O commands to multiple devices, then data processing throughput is improved, but I/O channel bottlenecks increase and resource management efficiency decreases

Engineering Contradiction:
Improvedata processing throughputVSAvoidI/O channel bottleneck
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements feedback by having device processors continuously monitor their own task execution status and delay risks, then report this information back to the host processor. The host processor uses this feedback to dynamically adjust I/O command issuance timing and distribution, optimizing throughput while preventing I/O channel bottlenecks through intelligent resource management.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system applies dynamics by making I/O scheduling flexible and adaptive rather than static. The host processor dynamically adjusts command timing and device allocation based on real-time device status and predicted completion times, allowing the system to maintain high throughput while adapting to varying device performance conditions.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the host device manages multiple devices independently, then device resource utilization is maximized, but overall system coordination efficiency decreases and task execution time increases

Engineering Contradiction:
Improvedevice resource utilizationVSAvoidtask execution coordination time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies segmentation by dividing the scheduling function into two parts: the device processor segments handle local task execution and self-monitoring, while the host processor segments handle global coordination and scheduling decisions. This segmentation allows devices to operate independently for resource utilization while the host provides efficient centralized coordination, reducing overall task execution time.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250291798A1IO scheduling method and device operating the same
Publication Date: 2025.09.18 SAMSUNG ELECTRONICS CO LTD
  • US20250291798A1 patent drawing
  • US20250291798A1 patent drawing
  • US20250291798A1 patent drawing

AI summary

IO scheduling method and device operating the same, are provided. A device connected to a host device through a CXL protocol, the device comprises a device memory which stores a query plan table and query plan status information synchronized with the host device and a device processor which processes a task according to the query plan table and updates query plan status information when receiving an operation command from the host.