CXL Data Link Layer Circuitry for Multi-Protocol Traffic
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Solution Overview
Problem
Current CXL interconnect technologies restrict the types of devices that can be connected to specific lanes of the link, limiting flexibility and requiring additional hardware resources for multiple protocol support.
Innovation Solution
A data link layer that supports multi-protocol message transmission, allowing flexible device attachment on interconnect lanes without additional silicon area or power consumption, using hardware autonomous and software-based techniques to configure link layer circuitry for CXL.cache and CXL.mem protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If device types are restricted on specific link lanes, then protocol compliance is maintained, but flexibility and adaptability are reduced
Solution Approach 1:
The link layer circuitry is designed to handle multiple protocols (CXL.cache, CXL.mem, CXL.io) through a unified processing pipeline. The same data link layer resources including buffers, error correction circuits, and control logic are shared across all protocol types, eliminating the need for protocol-specific hardware paths while maintaining compliance with each protocol's requirements through software-based configuration and control
2Reliability
If separate hardware resources are allocated for multiple protocols, then protocol performance is guaranteed, but silicon area and power consumption increase
Solution Approach 1:
The patent merges multiple protocol handling paths into a single shared data link layer pipeline. Buffers, error correction units, and control logic that would traditionally be duplicated for each protocol are instead shared resources. The CXL.cache and CXL.mem protocols share the same link layer circuitry, with protocol-specific behavior controlled through software configuration rather than hardware duplication
Solution Approach 2:
The link layer circuitry is designed as a universal processing unit that can handle different protocols through configuration rather than dedicated hardware paths. The same physical resources serve multiple protocol functions, reducing overall silicon area while maintaining performance guarantees through proper resource arbitration and protocol-aware control logic
3Measurement precision
If protocol-specific paths are used, then message routing accuracy is improved, but device complexity and hardware overhead increase
Solution Approach 1:
The patent introduces a control circuit as an intermediary between the shared buffer resources and the protocol-specific output paths. This control circuit receives protocol identification information, determines the appropriate routing path, and directs messages accordingly. This mediator approach maintains routing accuracy without requiring dedicated hardware paths for each protocol, as the routing decision is made dynamically based on protocol type rather than through fixed hardware connections
Data Source
AI summary
In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.