CXL Link Aggregation for Memory Coherency Management

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Solution Overview

Problem

Existing datacenter architectures face inefficiencies in managing link aggregation and memory sharing across multiple platforms, leading to suboptimal performance and increased complexity in data transfer and resource allocation.

Innovation Solution

Implementing the Compute Express Link (CXL) protocol for high-speed CPU-to-device and CPU-to-memory interconnects, enabling dynamic protocol multiplexing and memory pooling, and leveraging link aggregation to enhance data center performance by maintaining memory coherency and resource sharing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If link aggregation is implemented to increase bandwidth, then data transfer capacity is improved, but managing memory coherency and resource allocation becomes more complex

Engineering Contradiction:
Improvedata transfer capacityVSAvoidmemory coherency management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the link aggregation group into multiple individual links, each with its own memory cache. This segmentation allows independent management of coherence states for each link while maintaining the aggregated bandwidth benefit. The memory controller can selectively manage coherence on per-link basis rather than treating the entire aggregation as a single unit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces memory caches as intermediary components between the link aggregation layer and the memory coherence layer. These caches act as mediators that buffer coherence management complexity, allowing the system to maintain coherency across aggregated links without requiring complex centralized coordination. Each cache independently handles coherence for its associated link.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple memory caches are implemented for each link in aggregation, then link-specific coherence is improved, but hardware resource consumption increases

Engineering Contradiction:
Improvelink-specific coherenceVSAvoidhardware resource consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system implements memory caches for each link in the aggregation group, which may be more caches than strictly necessary if all links required full coherence support. This partial implementation provides coherence guarantees where needed while accepting that not all links will simultaneously require full coherence management, thereby reducing overall hardware resource consumption.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

Multiple link-specific memory caches are merged into a unified coherence management structure. The caches share common coherence control logic and can be coordinated through the memory controller, reducing the total hardware resources needed compared to completely independent coherence management for each link. The merging allows efficient use of cache memory space while maintaining link-specific coherence capabilities.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If a single memory cache is shared across all links in aggregation, then hardware resources are reduced, but coherence management becomes simpler

Engineering Contradiction:
Improvecoherence management simplicityVSAvoidhardware resource consumption
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

A single memory cache is designed with universal functionality to serve multiple links in the aggregation group. The cache can be selectively accessed by different links and maintains coherence states for data transferred over any of the aggregated links. This multi-functional approach reduces hardware resources while providing a unified coherence management interface that simplifies control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The single shared memory cache acts as a central intermediary for coherence management across all links in the aggregation. Rather than requiring complex inter-coordination between multiple independent caches, the shared cache provides a single point of coherence control that mediates between all links, simplifying the management architecture while reducing hardware complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260030164A1Link aggregation management
Publication Date: 2026.01.29 INTEL CORP
  • US20260030164A1 patent drawing
  • US20260030164A1 patent drawing
  • US20260030164A1 patent drawing

AI summary

A device, such as an I/O device, includes one or more ports to couple to one or more other devices, such as host devices, over two or more links, where the one or more ports include protocol circuitry to: implement a plurality of different link protocols, implement an aggregated link of the two or more links to couple to a given one of the one or more other devices, and manage a protocol resource based on the aggregated link.