CXL Memory Buffer for Multi-Device Map Data Management

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Solution Overview

Problem

The existing memory devices face limitations in managing large amounts of map data due to the limited capacity of buffer memories within storage devices, which restricts the implementation of high-capacity solid-state drives (SSDs) as the number of storage devices that can be connected with a host is limited by the interface, making it difficult to cope with increasing data capacities.

Innovation Solution

The proposed solution involves a memory device that communicates with multiple storage devices through a shared interface, using a CXL memory as a buffer to manage map data for each storage device, allowing for the allocation of a partial area of the CXL memory as a buffer for each device, thereby supporting high-capacity storage without the need for separate buffer memories within each storage device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If each storage device has its own buffer memory, then map data can be managed efficiently, but the number of storage devices that can be connected is limited by the host interface

Engineering Contradiction:
Improvenumber of storage devicesVSAvoidbuffer memory capacity
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Multiple storage devices share a common buffer memory resource through the CXL interface. The host device allocates buffer memory regions that can be accessed by multiple storage devices, consolidating what would traditionally be separate buffer memories into a shared resource. This enables more storage devices to be connected without each requiring dedicated buffer memory capacity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The CXL memory interface provides universal access to buffer memory regions across multiple storage devices. A single buffer memory region can serve multiple storage devices sequentially, making the buffer memory resource universal rather than dedicated to a single device. This multi-functional approach increases system capacity while maintaining performance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the host interface supports more storage devices, then high-capacity SSD can be implemented, but the interface complexity increases

Engineering Contradiction:
Improvedata capacityVSAvoidinterface complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The CXL interface acts as an intermediary between the host device and multiple storage devices. It provides a standardized protocol that simplifies the connection architecture, allowing the host to communicate with multiple storage devices through a single interface type. This mediator approach increases data capacity support without proportionally increasing interface complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system transitions from a single-device-per-interface model to a multi-device-per-interface model by adding a temporal dimension to buffer memory access. Instead of having parallel interfaces for each storage device, the system shares buffer memory regions across time, allowing multiple devices to access the same buffer memory at different times through the CXL interface.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentEP4273702A1Operating method of memory device for managing map data of each of plurality of storage devices, computing system including memory device, and operating method of computing system
Publication Date: 2023.11.08 SAMSUNG ELECTRONICS CO LTD
  • EP4273702A1 patent drawingFigure 1
  • EP4273702A1 patent drawingFigure 2
  • EP4273702A1 patent drawingFigure 3

AI summary

An operating method of a memory device which communicates with a first storage device and a second storage device through an interface circuit is provided. The method includes receiving, from a host device, a first request including a command and a first logical block address; obtaining, based on the first logical block address, a first physical block address with reference to first map data dedicated for the first storage device; and sending, to the first storage device through the interface circuit, a second request including the first physical block address and the command.