CXL Memory Disaggregation via Smart Switch Bypass
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Solution Overview
Problem
Conventional memory disaggregation methods, such as RDMA, suffer from slower performance due to unnecessary data copying and network processing, limiting the efficiency of memory resource utilization in data centers, while the Compute Express Link (CXL) standard has potential for memory aggregation but lacks a concrete hardware structure and memory aggregation method.
Innovation Solution
A memory disaggregation computing system using a direct CXL connection between a host server and a memory device, facilitated by a CXL switch, which maps memory resource information to a physical memory space, transmits memory requests as CXL packets, and processes responses without requiring software intervention for data copying, leveraging the CXL.io and CXL.mem protocols for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If RDMA methods are used for memory disaggregation, then memory resource utilization increases, but access speed decreases due to unnecessary data copying and network processing
Solution Approach 1:
The patent extracts and eliminates the unnecessary data copying step from the memory access process. By implementing a bypass mechanism that allows data to be transferred directly from remote memory to the CPU without being copied to intermediate buffers, the system maintains high memory resource utilization while significantly improving access speed.
Solution Approach 2:
The patent introduces a smart switch as an intermediary device that intelligently routes memory access requests. The switch acts as a mediator between the CPU and remote memory, determining whether to use the direct bypass path or the standard RDMA path based on the specific access pattern, thereby optimizing both speed and resource utilization.
2Speed
If CXL standard is used for memory disaggregation, then access speed improves by eliminating data copying, but hardware structure complexity increases
Solution Approach 1:
The patent segments the memory disaggregation system into distinct functional modules: the CXL controller, the smart switch, and the remote memory device. Each module has a specific responsibility, which simplifies the overall hardware structure by making it modular and easier to manage despite the increased complexity of the CXL standard.
Solution Approach 2:
The patent designs the CXL controller and smart switch to perform multiple functions. The CXL controller not only manages memory access but also handles protocol conversion and error correction. The smart switch provides both memory routing and direct bypass functionality. This multi-functionality reduces the need for additional dedicated hardware components, thereby controlling overall complexity.
3Speed
If direct CXL connection is implemented, then memory access performance approaches local memory speed, but system scalability is limited by connection constraints
Solution Approach 1:
The patent transitions from a single-dimension direct connection model to a multi-dimensional networked model using smart switches. This allows memory devices to be connected not only directly to a single CPU but also to multiple CPUs through the switch fabric, enabling the system to scale horizontally by adding more memory devices and CPUs without being constrained by direct connection limitations.
Solution Approach 2:
The smart switch serves as an intermediary that enables scalable system architecture. It mediates between multiple CPUs and memory devices, allowing any CPU to access any memory device through the switch network. This intermediary approach maintains high access performance by providing direct bypass paths while simultaneously enabling system scalability through its routing capabilities.
Data Source
AI summary
Disclosed is a memory disaggregation computing system including a host server and a memory device connected through a compute express link (CXL) network, in which a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource.