CXL Memory Controller ECC Predecoding for Faster Error Correction

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Solution Overview

Problem

Existing systems face challenges in efficiently managing and correcting errors in memory systems, particularly in shared memory environments where communication efficiency and access time are critical, due to the complexity of error bit mapping and correction.

Innovation Solution

A CXL memory controller incorporating a data conversion device that converts fail bit maps into error correction code (ECC) predecoded information, including address, error symbol position, and error type information, enabling efficient decoding and error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fail bit map is used for error correction in shared memory systems, then error correction capability is provided, but device complexity and processing overhead increase

Engineering Contradiction:

Improveerror correction capabilityVSAvoidcomplexity of error bit mapping and correction

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores error correction information in a lookup table during the manufacturing process. When an error occurs, the system simply queries the pre-stored information rather than performing complex real-time calculations, thereby reducing processing overhead and device complexity while maintaining error correction capability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates a simplified copy of the error correction data structure by converting the detailed fail bit map into a compressed representation that stores only essential error location and type information. This copied structure reduces the complexity of error bit mapping while preserving the necessary error correction functionality

Inventive Principle:

Principle #26Copying

2Reliability

If comprehensive error information is stored and processed, then error correction performance is improved, but access time increases

Engineering Contradiction:

Improveerror correction performanceVSAvoidaccess time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts only the critical error information (error location and type) from the comprehensive fail bit map and stores it in a compact format. This extraction allows the system to maintain high error correction performance by preserving essential data while reducing access time through a smaller, faster-to-query data structure

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

By pre-processing and storing error correction information in a lookup table during manufacturing, the system eliminates the need for complex real-time error analysis. This preliminary action enables fast access to error correction data without compromising correction performance

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP4700582A1CXL memory controller, operating method therefor, and CXL memory device

Publication Date: 2026.02.25 SAMSUNG ELECTRONICS CO LTD

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AI summary

A compute expression link (CXL) memory controller includes a data conversion device that receives a fail bit map and converts the fail bit map into error correction code (ECC) predecoded information in a symbol unit, a read only memory (ROM) that stores the ECC predecoded information, and an ECC engine that performs a decoding operation based on the ECC predecoded information. The ECC predecoded information includes address information indicating an address in which an error occurs, error symbol position information indicating one or more symbols in which the error occurs from among symbols corresponding to the address, and error type information indicating an error type of the one or more symbols.