CXL Memory Pooling Over Ethernet for Inter-Pod Disaggregation
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Solution Overview
Problem
Current CXL implementations in datacenters face limitations in deployment flexibility due to reliance on PCIe physical layers, which hinder the extension of memory pooling across inter-pod distances and lack mechanisms to bridge different physical address spaces, limiting scalability and flexibility in memory disaggregation solutions, especially in scenarios requiring dynamic memory allocation and distributed AI training.
Innovation Solution
The introduction of RPUs that translate CXL data over IEEE 802.3 PMA physical layers, enabling memory pooling infrastructure that leverages datacenter network fabric for intra-rack and inter-pod memory sharing, supporting various deployment scenarios including rack-level pooling, pod-scale distributed AI/ML training, and cloud-native memory-as-a-service architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If CXL implementations use PCIe physical layers, then memory disaggregation is enabled within racks, but deployment flexibility and scalability to inter-pod distances are limited
Solution Approach 1:
The patent enables CXL memory semantics to operate over multiple physical layer types (PCIe and IEEE 802.3 Ethernet), allowing the same CXL protocol stack to function across different distance scales and infrastructure types. This multi-functionality eliminates the need for separate infrastructure layers for intra-rack and inter-pod memory disaggregation.
Solution Approach 2:
The patent introduces intermediary devices (CXL switches, protocol translators) that bridge between PCIe-based CXL interconnects and IEEE 802.3-based Ethernet networks. These intermediaries maintain CXL semantics while translating physical layer protocols, enabling seamless extension from rack-scale to pod-scale deployments.
2Adaptability or versatility
If CXL semantics are extended across datacenter fabric, then memory pooling across pods is enabled, but challenges in maintaining coherency and performance arise
Solution Approach 1:
The patent segments the memory disaggregation system into hierarchical domains (rack-level CXL pools and pod-level CXL pools) with dedicated protocol translators at each boundary. This segmentation allows coherency to be maintained independently within each domain while enabling scalable expansion across multiple domains through standardized translation interfaces.
3Quantity of substance
If multiple infrastructure layers are deployed for memory disaggregation and networking, then rack-level memory pooling is achieved, but maintenance complexity increases
Solution Approach 1:
The patent merges memory disaggregation infrastructure with existing Ethernet networking infrastructure by enabling CXL protocols to run over IEEE 802.3 physical layers. This consolidation eliminates the need for separate PCIe switching fabric for memory pooling, reducing infrastructure complexity and maintenance burden while preserving memory resource capacity.
Data Source
AI summary
Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.