CXL Memory Expander for Host System Coherence

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Solution Overview

Problem

High availability systems with multiple host servers face inefficiencies in data synchronization due to the high CPU, memory, and network cycles required by side band protocols and RDMA, which can lead to performance bottlenecks and increased complexity.

Innovation Solution

Implementing a memory expander card with Compute Express Link (CXL) technology that enables coherent memory sharing between host systems, allowing direct access to a host managed device memory via CXL.mem and CXL.cache protocols, with a Field Programmable Gate Array (FPGA) for gatekeeping and synchronization, reducing the need for redundant data transfer and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If side band protocols or RDMA are used for data synchronization between primary and secondary host servers, then high availability and redundancy are achieved, but CPU cycles, memory cycles, and network cycles increase significantly

Engineering Contradiction:
Improvehigh availabilityVSAvoidCPU and memory cycles
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

A shared device memory pool acts as an intermediary between primary and secondary host servers, enabling direct memory access for data synchronization. This eliminates the need for complex side band protocols and RDMA operations, significantly reducing CPU and memory cycle consumption while maintaining high availability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent merges the memory resources of multiple host servers into a single shared device memory pool. This consolidation allows both primary and secondary hosts to access the same memory space directly, eliminating redundant data transfer operations and reducing overall system resource consumption

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If side band protocols are used for data synchronization, then redundancy data is transferred between host servers, but device complexity and software overhead increase

Engineering Contradiction:
ImproveredundancyVSAvoidsoftware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shared device memory pool serves as a simplified intermediary that provides direct access to redundancy data. This eliminates complex software stacks and protocols, reducing device and software complexity while maintaining comprehensive redundancy coverage

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system enables self-service data synchronization through direct memory access. The secondary host can directly access and retrieve redundancy data from the shared device memory pool without requiring complex coordination software or protocol handling, significantly simplifying the system architecture

Inventive Principle:
Principle #25Self-service

3Reliability

If traditional synchronization methods are used, then data is transferred between host servers, but communication speed and efficiency decrease

Engineering Contradiction:
Improvedata synchronizationVSAvoidcommunication speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent extracts data synchronization operations from the traditional network protocol stack and places them directly in the memory space. By taking out the intermediate protocol handling and enabling direct memory access, the system achieves significantly faster communication speeds while maintaining reliable data synchronization

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240176740A1Host managed memory shared by multiple host systems in a high availability system
Publication Date: 2024.05.30 ALTERA CORP
  • US20240176740A1 patent drawing
  • US20240176740A1 patent drawing
  • US20240176740A1 patent drawing

AI summary

A high availability system including multiple host systems includes a host managed device memory that is shared between the multiple host systems allowing faster communication between the host systems. Access to the host managed device memory in a memory expander card is via direct memory access from the host system. Memory expander card control circuitry in the memory expander card performs memory translation, gatekeeping and synchronization. A host system can access the host managed device memory in the memory expander card directly using cxl.cache and cxl.mem protocols. From the host system perspective, the host managed device memory in the memory expander card is directly attached using a memory mapped interface.