CXL Memory Module Architecture for Capacity Expansion and Bandwidth
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Solution Overview
Problem
Existing technologies fail to effectively address the challenge of enhancing memory capacity and bandwidth, particularly in scenarios involving memory modules, which hinders the development of high-performance computing and AI computing.
Innovation Solution
A memory module and an electronic device comprising a memory module and an electronic device, which includes a memory module and an electronic device comprising a memory module and an electronic device, which includes a memory module and an electronic device, which includes a memory module and an electronic device comprising a memory module and an electronic device, which includes a memory module and an electronic device comprising a memory module and an electronic device, which includes a memory module and an electronic device comprising a memory expander controller chips, a PCIe golden finger, a MCIO connector, and a DIMM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is expanded using traditional methods, then memory capacity increases, but performance is sacrificed
Solution Approach 1:
The patent divides the memory expansion function into multiple MXC chips, each capable of independently managing memory resources. Each MXC chip can be configured with different bandwidth capabilities (e.g., 8-bit, 16-bit interfaces), allowing the system to expand capacity while maintaining high performance through parallel processing and selective use of high-bandwidth channels.
Solution Approach 2:
The MXC chips are designed with multi-functional capabilities, supporting both high-capacity memory expansion and high-performance data transfer through dual interfaces (PCIe and MCIO). This universal design allows the same hardware component to serve multiple purposes: expanding capacity via additional memory channels while maintaining performance through high-speed interfaces.
2Quantity of substance
If memory capacity is increased, then more memory is available, but bandwidth per core declines
Solution Approach 1:
The patent introduces a new dimensional approach by implementing multi-channel memory architecture with MXC chips that provide multiple independent data paths. Instead of increasing capacity through a single bottlenecked channel, the system adds spatial dimensions of data transfer through parallel channels (PCIe x16, MCIO x16), thereby increasing capacity while maintaining or even improving bandwidth per core through distributed data paths.
3Quantity of substance
If multiple MXC chips are used to expand memory capacity, then memory capacity increases, but device complexity increases
Solution Approach 1:
The patent merges multiple MXC chips into a unified memory module architecture that presents a single logical interface to the host system. The MXC chips are interconnected through standardized interfaces (PCIe, MCIO, DDR5 controller ports), allowing them to function as an integrated unit. This merging approach enables capacity expansion while managing complexity through modular design and standardized interconnections.
Solution Approach 2:
The patent introduces intermediary components including memory controllers, PCIe switches, and standardized connectors that mediate between multiple MXC chips and the host system. These intermediaries manage the complexity of multi-chip configurations by providing standardized interfaces, signal routing, and protocol handling, thereby enabling capacity expansion without proportionally increasing system complexity.
4Adaptability or versatility
If traditional memory module architecture is used, then compatibility is maintained, but memory capacity and bandwidth scalability are limited
Solution Approach 1:
The patent implements a universal memory module architecture that maintains compatibility with existing server platforms through standardized interfaces (PCIe, DDR5) while simultaneously providing enhanced capacity and bandwidth scalability. The MXC chips can be configured in various combinations (different numbers of chips, different interface types) to accommodate different capacity requirements while maintaining compatibility with standard server motherboards and memory slots.
Data Source
AI summary
The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input/output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.