CXL Memory Module With Direct Cluster Links to Reduce Wiring
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Solution Overview
Problem
Computing systems face bottlenecks in data processing speed due to communication constraints between host devices and storage devices, limiting the effective bandwidth and memory capacity.
Innovation Solution
Implementing a memory module with a substrate, allocator, and memory cluster packages connected via serial communication lanes, utilizing a Compute Express Link (CXL) interface to enhance communication efficiency and reduce wiring overhead, allowing direct communication between memory cluster packages without passing through the allocator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional parallel communication interfaces are used between host device and storage device, then data processing speed can be improved, but the number of pins and wiring complexity increase significantly
Solution Approach 1:
The patent replaces traditional parallel mechanical pin connections with a serial communication interface based on CXL (Compute Express Link) protocol. This substitution reduces the physical connection complexity from multiple parallel pins to a single serial communication lane, while maintaining high data processing speed through efficient serial data transmission protocols.
2Productivity
If multiple memory channels are implemented to increase effective bandwidth, then data processing speed improves, but the number of pins required increases
Solution Approach 1:
The patent transitions from parallel communication dimension to serial communication dimension. Instead of using multiple parallel pins to achieve higher bandwidth, the system uses a single serial communication lane that achieves the same or higher bandwidth through time-division multiplexing and efficient data encoding protocols, thereby reducing the pin count while maintaining productivity.
3Loss of time
If direct communication between memory cluster packages is enabled, then communication overhead is reduced, but the communication path becomes more complex
Solution Approach 1:
The patent introduces a memory controller as an intermediary component that manages communication between memory cluster packages. This intermediary enables direct communication paths while providing necessary protocol handling, address translation, and data buffering functions, thereby reducing communication overhead without creating unacceptable complexity in the communication path.
Data Source
AI summary
A memory module includes a substrate, an allocator, memory cluster packages and serial communication lanes. The allocator is mounted on the substrate, and communicates with an external device through a CXL interface. The memory cluster packages are mounted on the substrate, and are controlled by the allocator. Each of the memory cluster packages includes memories and a memory controller. The serial communication lanes are disposed on the substrate for communications between the allocator and the memory cluster packages. A first memory cluster package communicates with the allocator through a first serial communication lane and the serial interface. A second memory cluster package communicates with the first memory cluster package through a second serial communication lane and the serial interface.