CXL Memory Module Prefetch Controller for Host Access Patterns

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Solution Overview

Problem

Current memory modules lack an efficient mechanism to prefetch or evict data based on host access patterns, leading to suboptimal performance and resource utilization.

Innovation Solution

A memory module with a memory controller that uses a Compute Express Link (CXL) interface, incorporating a cache memory, map management data storage, and a prefetch controller to analyze access patterns and prioritize data prefetching through algorithms like temporal, spatial, and sequential locality algorithms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data prefetching is implemented without access pattern analysis, then memory access speed is improved, but memory bandwidth is wasted due to prefetching unnecessary data

Engineering Contradiction:

Improvememory access speedVSAvoidmemory bandwidth waste

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent implements preliminary action by prefetching data into the memory module before the host actually requests it. The prefetch controller analyzes access patterns and proactively loads candidate data into the buffer memory, so that when the host needs the data, it is already available, thus improving memory access speed without wasting bandwidth on unnecessary transfers.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback by continuously monitoring the host's access patterns and using this information to guide prefetching decisions. The prefetch controller receives feedback about which data the host accesses and when, then uses this feedback to predict future access needs and adjust prefetching strategies accordingly, preventing bandwidth waste on unnecessary data while maintaining fast access speed.

Inventive Principle:

Principle #23Feedback

2Measurement precision

If multiple algorithms are used to calculate prefetch priority, then data prefetching accuracy is improved, but device complexity increases

Engineering Contradiction:

Improveprefetch priority accuracyVSAvoidprefetch controller complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the prefetch controller into multiple independent algorithm modules, each responsible for a specific prefetching strategy (e.g., temporal locality, spatial locality, sequential access patterns). This segmentation allows the system to use multiple algorithms for accurate prefetch priority calculation while managing complexity through modular design, where each algorithm can be independently configured and tuned.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20240385968A1Memory module, memory system including memory module, and method of operating the same

Publication Date: 2024.11.21 SK HYNIX INC

AI summary

The present technology relates to an electronic device. According to the present technology, a memory module communicating with a host through a compute express link (CXL) interface includes a non-volatile memory device, a volatile memory device and a memory controller. The non-volatile memory device may store data. The memory controller may select candidate data to be prefetched among the data based on access pattern information of the host for the data and a plurality of algorithms, and prefetch target data among the candidate data to the volatile memory device.