CXL Memory Aggregation for Low-Latency RDMA Across Servers

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Solution Overview

Problem

Existing server systems face challenges in efficiently managing memory resources across multiple servers while minimizing the involvement of processing resources, particularly in scenarios where remote direct memory access (RDMA) is required.

Innovation Solution

Implementing a system that utilizes Compute Express Link (CXL) connections and enhanced capability CXL switches to aggregate memory resources, enabling cache-coherent protocols for heterogeneous processing, virtualize memory, and support RDMA operations without significant involvement from processing circuits, using a fabric manager to manage device discovery and virtualization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory resources are aggregated across multiple servers using traditional methods, then memory capacity is increased, but processing overhead and latency increase

Engineering Contradiction:
Improvememory capacityVSAvoidaccess latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent introduces CXL switches as intermediary devices that manage memory aggregation across servers. These switches provide a fabric-based communication medium that enables remote memory access with reduced latency compared to traditional network protocols, while maintaining cache coherence through specialized hardware support.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces traditional network-based memory access mechanisms (which rely on software processing and network protocols) with a specialized CXL fabric system that uses hardware-accelerated protocols. This substitution eliminates software processing overhead and reduces access latency through dedicated hardware paths.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If processing resources are involved in memory management operations, then memory access control is improved, but processing resource utilization increases

Engineering Contradiction:
Improvememory access controlVSAvoidprocessing resource utilization
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements self-service memory management where the CXL fabric and switches autonomously handle memory access control, address translation, and cache coherence maintenance. This eliminates the need for processing resources to intervene in routine memory operations, allowing processors to focus on compute-intensive tasks while the fabric manages memory operations independently.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If traditional network protocols are used for inter-server communication, then system compatibility is maintained, but memory access efficiency decreases

Engineering Contradiction:
Improvesystem compatibilityVSAvoidmemory access efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent designs the CXL fabric to provide multi-functional capabilities that work across different server architectures and memory types. The fabric supports both traditional network protocols and specialized CXL protocols, enabling it to adapt to various system configurations while maintaining high performance through hardware-accelerated paths for memory-intensive operations.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3916565B1System and method for aggregating server memory
Publication Date: 2026.04.22 SAMSUNG ELECTRONICS CO LTD
  • EP3916565B1 patent drawingFigure 1A
  • EP3916565B1 patent drawingFigure 1B
  • EP3916565B1 patent drawingFigure 1C

AI summary

A system and method for managing memory resources. In some embodiments, the system includes a stored-program processing circuit, a network interface circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the network interface circuit, and the stored-program processing circuit is connected to the cache-coherent switch.