CXL Memory Subsystem for Persistent Region Access
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Solution Overview
Problem
Current memory sub-systems with persistent memory regions (PMR) face limitations in cacheability, coherency, and scalability, making them less useful for transaction-oriented applications due to potential lack of cacheability and coherency, requiring custom software, and having limited performance and small memory sizing.
Innovation Solution
A memory sub-system that combines a storage element on a non-volatile memory device with a PMR on a volatile memory device, utilizing the Compute Express Link (CXL) interface standard to provide enhanced access, enabling byte-addressable memory alongside block storage with increased cacheability and coherency, and supporting both volatile and persistent memory architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If persistent memory region (PMR) is implemented on volatile memory device, then access speed is improved, but cacheability and coherency are worsened
Solution Approach 1:
The memory system is segmented into distinct volatile memory region and persistent memory region, each with different access characteristics. The volatile memory provides fast access while the persistent memory ensures data durability. This segmentation allows the system to simultaneously achieve high-speed access for frequently accessed data and reliable persistence for critical data.
Solution Approach 2:
A memory controller acts as an intermediary between the host system and the memory devices, managing cacheability and coherency protocols. The controller translates host memory access requests into appropriate operations for volatile or persistent memory, maintaining cache coherence without exposing the complexity to the host system.
2Ease of operation
If custom software is used to manage PMR access, then access control is improved, but device complexity is worsened
Solution Approach 1:
The memory subsystem implements self-service mechanisms through hardware-managed address translation and memory management functions. The device automatically handles address mapping, cache management, and data persistence without requiring custom host software, reducing system complexity while maintaining secure access control.
Solution Approach 2:
The memory controller provides universal interface support for both volatile and persistent memory operations through a single standardized interface. This multi-functional approach eliminates the need for separate custom software drivers for different memory types, simplifying the software stack while providing comprehensive access control.
3Quantity of substance
If PMR size is limited, then device cost is reduced, but memory capacity is worsened
Solution Approach 1:
The system merges volatile memory and persistent memory into a single unified memory device, combining the high-speed access of volatile memory with the data persistence of non-volatile memory. This integration provides large total memory capacity with a portion dedicated to persistent storage, achieving both capacity and cost-effectiveness through shared device infrastructure.
Solution Approach 2:
The persistent memory region is nested within the larger memory device structure, with the volatile memory region containing or overlapping the persistent memory region. This nested architecture allows the system to provide extended memory capacity while maintaining cost efficiency through shared physical infrastructure and control logic.
4Productivity
If PMR access latency is reduced, then performance is improved, but cacheability is worsened
Solution Approach 1:
The memory system dynamically adjusts access paths and caching strategies based on data characteristics and access patterns. Frequently accessed data is automatically cached in volatile memory for low-latency access, while less frequently accessed data resides in persistent memory. This dynamic management achieves high performance for active data while maintaining cacheability for frequently accessed information.
Solution Approach 2:
The system changes memory access parameters such as cache line size, cache associativity, and replacement policies to optimize both latency and cacheability. By adjusting these parameters based on workload characteristics, the system achieves low latency for performance-critical operations while maintaining effective caching for data that benefits from cacheability.
Data Source
AI summary
A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.