CXL Memory Tiering with Adaptive RAID and Compression

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Solution Overview

Problem

Computer systems face challenges in achieving high-capacity and high-speed memory while maintaining reliability, as faster memories are more expensive and occupy larger areas, and their characteristics change over time, affecting reliability in hierarchical memory systems.

Innovation Solution

The implementation of CXL devices with an adaptive RAID structure and operation methods that classify memories into tier groups based on metadata, using RAID 0 and nested RAID structures for different tiers, and employing compression algorithms to optimize data storage and retrieval based on usage ratios and speed requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed memory is used to achieve high input/output speed, then input/output speed is improved, but cost increases and area occupied increases

Engineering Contradiction:
Improveinput/output speedVSAvoidmemory area
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The memory system is segmented into multiple tiers with different performance characteristics. High-speed memory (first tier) handles frequently accessed data, while lower-speed memory (second tier) stores less frequently accessed data. This segmentation allows the system to achieve high input/output speed for critical data without requiring all memory to be high-speed, thus reducing overall memory area and cost.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the memory hierarchy are assigned different quality levels. The first tier uses high-speed memory with superior performance characteristics, while the second tier uses lower-speed memory. This local quality differentiation ensures that high input/output speed is provided where needed (for hot data) without incurring the cost and area of high-speed memory throughout the entire system.

Inventive Principle:
Principle #3Local quality

2Speed

If high-speed memory is used to achieve high input/output speed, then input/output speed is improved, but cost increases

Engineering Contradiction:
Improveinput/output speedVSAvoidmemory cost
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The memory system is divided into tiers with different cost and performance characteristics. By placing only the most frequently accessed data in expensive high-speed memory, the system achieves high input/output speed for critical operations while minimizing the total cost of memory resources.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically changes parameters such as memory tier assignment and RAID configuration based on data access patterns. When data is frequently accessed, it is placed in higher-tier memory to improve input/output speed. This dynamic parameter adjustment allows the system to optimize between speed and cost based on actual usage patterns.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If memory characteristics are allowed to change over time, then memory capacity utilization is improved, but reliability is affected

Engineering Contradiction:
Improvememory capacity utilizationVSAvoiddata reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The memory hierarchy is designed to be dynamic, with data automatically migrated between tiers based on access patterns and memory characteristics. This dynamic adaptation improves capacity utilization by placing data in the most appropriate storage tier. Meanwhile, RAID structures provide redundancy to maintain reliability despite these dynamic changes and potential memory failures.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

RAID (Redundant Array of Independent Disks) structures are implemented across the memory tiers to provide beforehand cushioning against memory failures. Parity information is pre-calculated and stored, so that if a memory module fails or characteristics degrade, data can be recovered without loss, thus maintaining reliability while allowing memory characteristics to change over time.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If RAID structure is implemented to protect data, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata protectionVSAvoidmemory management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The RAID implementation is segmented and applied selectively across different memory tiers rather than uniformly throughout the entire memory system. This allows data protection to be provided where most needed while reducing the overall complexity of memory management by not applying RAID to all memory operations.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240168848A1CXL devices and operation methods of CXL devices
Publication Date: 2024.05.23 SAMSUNG ELECTRONICS CO LTD
  • US20240168848A1 patent drawing
  • US20240168848A1 patent drawing
  • US20240168848A1 patent drawing

AI summary

Embodiments of the present invention provide a CXL device including a plurality of memories; a memory management unit configured to: configure at least one tier group in which the plurality of memories are classified and included; determine, based on metadata of a first memory of the plurality of memories, a grade of the first memory; and determine a tier group, to which the first memory belongs, of the at least one tier group according to the grade; and a memory processing unit configured to store data in at least one of the plurality of memories included in the at least one tier group, based on tiering information of the data.