CXL Multiplexor Circuitry for Parallel Device Testing
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Solution Overview
Problem
Existing processors that only support up to CXL 1.1 are limited in their ability to take advantage of improved CXL bus protocol enhancements, specifically in multi-port testing, which restricts testing parallelism and efficiency to 16 lanes in parallel.
Innovation Solution
The implementation of multiplexor circuitry between the CXL 1.1 CPU and the DUTs allows for selective configuration of 16 lane (×16) or 8 lane (×8) testing, enabling improved parallelism and testing efficiency by utilizing all available lanes under the enhanced CXL bus protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CXL 1.1 processors are used with existing test approaches, then compatibility with existing processors is maintained, but testing parallelism is limited to 16 lanes in parallel
Solution Approach 1:
The patent introduces multiplexor circuitry as an intermediary component between the CXL 1.1 processor and the DUTs. This multiplexor enables the processor to dynamically switch between different bus lane configurations (16 lanes for single DUT or 8 lanes for multiple DUTs), thereby achieving CXL 2.0 level parallelism while maintaining compatibility with CXL 1.1 processors.
Solution Approach 2:
The patent implements dynamic reconfigurability by allowing the multiplexor circuitry to switch between different operational modes. The system can dynamically adjust the number of active bus lanes and the number of DUTs being tested simultaneously, transforming a static testing system into a dynamic one that adapts to different testing scenarios.
2Productivity
If 16 lanes are used for testing single DUT, then testing efficiency for that DUT is maximized, but number of DUTs that can be tested in parallel is reduced
Solution Approach 1:
The patent segments the 16 bus lanes into configurable groups that can be dynamically allocated. The multiplexor divides the 16 lanes into either a single 16-lane channel for one DUT or multiple 8-lane channels for multiple DUTs, allowing flexible segmentation of testing resources based on the number and priority of DUTs being tested.
Solution Approach 2:
The system dynamically adjusts the lane allocation strategy based on testing priorities and available DUTs. When fewer DUTs are present, the system concentrates lanes on fewer DUTs for faster testing. When more DUTs are present, it distributes lanes across multiple DUTs to maximize parallel throughput.
3Productivity
If multiplexor circuitry is added to enable 16 lane testing, then testing parallelism is improved, but device complexity increases
Solution Approach 1:
The multiplexor circuitry serves as a compact intermediary that sits between the processor and the DUTs, consolidating the complexity into a single integrated component. This approach avoids the need for multiple separate test systems or complex reconfiguration of the entire testing architecture.
Solution Approach 2:
The multiplexor circuitry performs multiple functions: it acts as a signal switch, a lane allocator, and a configuration controller all in one component. This multi-functional design achieves high parallelism capability while minimizing the overall complexity increase compared to implementing separate dedicated circuits for each function.
Data Source
AI summary
Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.