CXL Peer-to-Peer Memory Access Requests Without Host Mediation

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Solution Overview

Problem

Existing CXL devices require a host system as an intermediary for peer-to-peer memory access requests, leading to increased latency and inefficient bandwidth utilization.

Innovation Solution

CXL devices are enabled to directly communicate memory access requests through a CXL.io interface using Base Address Registers (BARs) to access local address spaces of other CXL devices, bypassing the host system intermediary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If CXL devices use host system as an intermediary for peer-to-peer memory access requests, then the system maintains simplified control and address translation, but the access latency increases and bandwidth utilization decreases

Engineering Contradiction:

Improvememory access latencyVSAvoidcommunication path complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent extracts the host system intermediary from the memory access path between CXL devices. By enabling direct peer-to-peer access through CXL.io interface, the host system is removed from the critical data access path, eliminating the additional latency introduced by host-mediated address translation and command routing, while maintaining host control through separate management channels

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the CXL system into independent communication domains: direct peer-to-peer data access paths using CXL.io interface, and separate host management paths. This segmentation allows optimized direct access for performance-critical operations while maintaining simplified host control for address translation and memory management, resolving the contradiction between speed and control

Inventive Principle:

Principle #1Segmentation

2Productivity

If CXL devices communicate through host system intermediary, then address translation and memory management are simplified, but bandwidth between CXL devices is reduced

Engineering Contradiction:

Improvebandwidth between CXL devicesVSAvoidaddress translation simplicity

Core Design Contradiction:

ProductivityVSEase of operation

Solution Approach 1:

The patent introduces a peer device as a direct intermediary in the memory access path, replacing the host system intermediary. CXL devices can directly translate addresses and route memory access requests through the CXL.io interface, eliminating the bandwidth bottleneck of host-mediated communication while maintaining address translation functionality at the device level

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent adds a direct peer-to-peer communication dimension to the traditional host-mediated access model. By implementing dual paths (direct CXL.io access and host-mediated access), the system achieves high bandwidth through direct paths for data-intensive operations while preserving address translation simplicity through host management for control-plane operations

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250225084A1Peer-to-peer memory access request for memory devices

Publication Date: 2025.07.10 MICRON TECHNOLOGY INC

AI summary

A memory access request is initiated by a first peripheral device. The memory access request includes a virtual address. A host physical address (HPA) associated with the virtual address is determined. An identifier of a base address register (BAR) associated with the HPA is determined by the first peripheral device. The memory access request is transmitted using the identifier of the BAR to a second peripheral device.