CXL Persistent Byte-Addressable Memory for Power Loss Recovery
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Solution Overview
Problem
Existing memory systems face inefficiencies in power loss recovery due to the delay in data storage and retrieval, leading to potential data loss during asynchronous power loss events, especially when using non-volatile memory devices, as traditional capacitors provide limited power and require inefficient prioritization of system components during power loss.
Innovation Solution
Implementing a persistent byte-addressable memory (PBAM) in a compute express link (CXL) memory device with a smaller data granularity, allowing data to be stored in small packets in a non-volatile PBAM layer, which can be completed or resent upon power restoration, ensuring efficient power loss recovery and minimizing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional capacitors are used for power loss recovery, then limited power is provided to maintain system operation, but inefficient prioritization of system components occurs and data loss risk increases
Solution Approach 1:
The patent segments the memory system into multiple layers: a persistent byte-addressable memory (PBAM) layer for critical data storage and a traditional non-volatile memory layer for bulk storage. This segmentation allows the system to prioritize recovery of frequently accessed data in the PBAM layer during power loss events, reducing overall recovery time while maintaining reliability.
Solution Approach 2:
The patent implements preliminary action by pre-storing critical data in the PBAM layer before power loss occurs. The byte-addressable nature of PBAM allows for granular data protection, where only the specific bytes affected by power loss need to be recovered, rather than recovering entire blocks or pages. This preliminary positioning of data enables faster recovery without requiring full system reboot.
2Reliability
If non-volatile memory devices are used for data storage, then data retention is improved during power loss, but data access speed decreases
Solution Approach 1:
The patent applies local quality by creating a PBAM layer with byte-addressable access characteristics for frequently accessed data, while maintaining traditional block-addressable non-volatile memory for bulk storage. This allows the system to have fast, granular access to critical data locally in the PBAM layer while preserving the high capacity and data retention of non-volatile memory for less frequently accessed data.
Solution Approach 2:
The patent implements a nested memory architecture where the PBAM layer is nested within or alongside the traditional non-volatile memory layer. The PBAM provides byte-addressable access to portions of the data stored in the non-volatile memory, creating a hierarchical structure that combines the speed and granularity of volatile memory with the persistence of non-volatile memory.
3Productivity
If byte-addressable persistent memory is implemented, then data granularity is reduced for faster recovery, but device complexity increases
Solution Approach 1:
The patent introduces a controller as an intermediary between the host system and the nested memory layers. This controller manages the complexity of the PBAM layer by handling byte-addressable access requests, translating them into appropriate operations on the underlying non-volatile memory when necessary. The intermediary absorbs the complexity, presenting a simplified interface to the host while enabling fine-grained recovery capabilities.
4Device complexity
If traditional block-addressable memory is used, then device complexity is reduced, but data loss impact increases during power loss
Solution Approach 1:
The patent segments data storage into the PBAM layer for critical, frequently accessed data and the traditional non-volatile memory layer for bulk storage. This segmentation ensures that only the small portion of data in the PBAM layer needs to be protected against power loss with byte-level granularity, rather than protecting entire blocks. This reduces the overall data loss impact while maintaining manageable device complexity.
Data Source
AI summary
A system can include a first memory device including a persistent byte-addressable memory; a second memory device; and a processing device, operatively coupled with the first and second memory devices, to perform operations including: receiving a first host command to write or read user data; storing the user data in the persistent byte-addressable memory with a first data granularity; and transmitting the user data stored in the persistent byte-addressable memory to the second memory device. The operations can further include: responsive to determining that a power loss event has occurred during an operation to a particular data packet in a size of the first data granularity in the persistent byte-addressable memory, determining whether the first host command associated with the particular data packet is completely executed; and responsive to determining that the first host command is not completely executed, restoring the particular data packet in the persistent byte-addressable memory.