CXL.mem-to-CXL.cache Translation for Direct Host Communication
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Solution Overview
Problem
The CXL Specification (Revision 3.1) lacks support for direct host-to-host communication using CXL.cache or CXL.mem protocols, hindering the development of fully disaggregated memory-centric architectures where multiple hosts can share and access disaggregated memory resources over their native CXL interfaces.
Innovation Solution
Implementing a Resource Provisioning Unit (RPU) to translate between CXL.mem and CXL.cache write transactions, enabling different hosts to communicate using native memory and cache semantics, allowing for flexible data sharing and memory access models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CXL Specification (Revision 3.1) is used for memory access, then memory pooling and sharing capabilities are provided, but direct host-to-host communication using CXL.cache or CXL.mem protocols is not supported
Solution Approach 1:
The patent introduces an intermediary device (CXL Type 2 or Type 3 device) that acts as a protocol translator between hosts using different CXL protocols. This intermediary receives CXL.mem transactions from one host, translates them into CXL.cache transactions, and forwards them to the target host, thereby enabling host-to-host communication without requiring both hosts to support the same protocol natively.
2Adaptability or versatility
If CXL.mem protocol is used for memory access, then memory pooling is enabled, but cache-coherent access to shared memory between hosts is limited
Solution Approach 1:
The patent changes the protocol parameters (from CXL.mem to CXL.cache) during translation while maintaining the essential memory access semantics. The translation process preserves cache coherence by mapping CXL.mem memory access patterns into equivalent CXL.cache operations, ensuring that cache coherence requirements are met despite the protocol transformation.
3Speed
If legacy IO-fabric solutions like PCIe are used, then broad compatibility is achieved, but high-speed communication and memory disaggregation potential are not fully exploited
Solution Approach 1:
The patent creates a universal translation layer that enables multiple CXL protocol types (CXL.mem, CXL.cache) to interoperate through a common intermediary. This multi-functional approach allows the system to support both memory pooling (CXL.mem) and cache-coherent access (CXL.cache) through the same infrastructure, maximizing the utility of the CXL fabric without requiring separate dedicated paths for each protocol type.
Data Source
AI summary
Embodiments for communicating between first and second hosts according to CXL.mem and CXL.cache protocols. A computer translates a CXL.mem M2S RwD with a Tag, received by a CXL Type 2 or Type 3 device (EP1) from the first host, to a CXL.cache D2H Req with a CQID. A CXL Type 1 or Type 2 device (EP2) sends the D2H Req to the second host, and receives a CXL.cache H2D Rsp with the CQID and a UQID. EP1 sends a CXL.mem S2M NDR with the Tag to the first host, and EP2 sends a CXL.cache D2H Data message with the UQID to the second host. Optionally, EP1 receives and terminates CXL.io/PCIe Configuration Request TLPs from the first host, the M2S RwD further includes a first physical address and Data, and the D2H Req further includes a second physical address.